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High-speed CMOS multiplexer

  • US 6,194,950 B1
  • Filed: 08/28/1998
  • Issued: 02/27/2001
  • Est. Priority Date: 08/28/1997
  • Status: Expired due to Term
First Claim
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1. A time division CMOS multiplexer having input terminals to receive at least two input signals and an output terminal that outputs a multiplexed signal, comprising:

  • an integrated circuit comprising;

    CMOS voltage control means for generating a voltage controlled oscillator signal having a frequency;

    CMOS multiplexing means for receiving the oscillator signal having the frequency for multiplexing the at least two input signals and outputting the multiplexed signal, wherein the CMOS multiplexing means consists essentially of inverters and pass gates and synchronizing means for synchronizing the voltage controlled oscillator signal and the at least two input signals.

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