Low critical voltage current mirrors

• US 6,194,956 B1
• Filed: 04/29/1999
• Issued: 02/27/2001
• Est. Priority Date: 05/01/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Barnes, William Bryan
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/304,209
• Time in Patent Office: 670 Days
• Field of Search: 327/53, 327/538, 327/541, 327/543, 330/288, 323/312, 323/314, 323/315
• US Class Current: 327/538
• CPC Class Codes: G05F 3/262 using field-effect transistors only

Abstract

A current mirror has an input node for receiving an input current and an output node for providing an output current. First, second and third transistors are provided with each transistor having first and second current path terminals and a control terminal. The control terminals of the first and second transistors are connected to each other. The first current path terminal of the first transistor and one of the current path terminals of the second transistor are connected to a power supply. The control terminal of the third transistor is connected to the input node. One of the first and second current path terminals of the third transistor are connected to the output node and the other of the first and second current path terminals of the third transistor are connected to the other of the first and second current path terminals of the second transistor. A resistive element is arranged between the input node and the second current path terminal of the first transistor. The control terminals of the first and second transistors are connected to a node between the resistive element and a second current path terminal of the first transistor. The resistive element is a transistor of the opposite polarity to the first, second and third transistors.

Claims

1. A current mirror comprising:

an input node for receiving an input current;

an output node for providing an output current;

first, second and third transistors, each transistor comprising first and second current path terminals and a control terminal, the control terminals of the first and second transistors being connected to each other, the first current path terminal of the first transistor and one of the current path terminals of the second transistor being connected to a power supply, the control terminal of the third transistor being connected to the input node, one of the first and second current path terminals of the third transistor being connected to the output node and the other of the first and second current path terminals of the third transistor being connected to the other of the first and second current path terminals of the second transistor; and

a resistive element connected in series between the input node and the second current path terminal of the first transistor, the control terminals of the first and second transistors being connected to a node between the resistive element and the second current path terminal of said first transistor, said resistive element being a transistor of the opposite polarity to the first, second and third transistors.

2. A current mirror as claimed in claim 1 wherein a control terminal of the transistor comprising the resistive element is connected to a power source.

3. A current mirror as claimed in claim 1, wherein said first, second and third transistors are n-type transistors.

4. A current mirror as claimed in claim 1, wherein a fourth transistor is provided with one of its current path terminals connected to the second current path terminal of the first transistor and the other of the first and second current path terminals of the fourth transistor connected to one end of the resistive element.

5. A current mirror as claimed in claim 4, wherein the control terminal of the fourth transistor is connected to the control terminal of the third transistor.

6. A current mirror as claimed in claim 4, wherein said fourth transistor is connected between the second terminal of the first transistor and the input node.

7. A current mirror as claimed in claim 4, wherein said fourth transistor has the same polarity of the first, second and third transistors.

8. A current mirror as claimed in claim 4, wherein said fourth and third transistors are matched.

9. A current mirror as claimed in claim 1, wherein said first and second transistors are matched.

10. A current mirror as claimed in claim 1, wherein said transistors are field effect transistors.

11. A current mirror as claimed in claim 10, wherein said transistors are MOSFETs.

12. A current mirror as claimed in any one of claim 1, wherein said transistors are bipolar transistors.

13. An integrated circuit including a current mirror comprising:

an input node for receiving an input current;

an output node for providing an output current;

first, second and third transistors, each transistor comprising first and second current path terminals and a control terminal, the control terminals of the first and second transistors being connected to each other, the first current path terminal of the first transistor and one of the current path terminals of the second transistor being connected to a power supply, the control terminal of the third transistor being connected to the input node, one of the first and second current path terminals of the third transistor being connected to the output node and the other of the first and second current path terminals of the third transistor being connected to the other of the first and second current path terminals of the second transistor; and

a resistive element connected in series between the input node and the second current path terminal of the first transistor, the control terminals of the first and second transistors being connected to a node between the resistive element and the second current path terminal of said first transistor, said resistive element being a transistor of the opposite polarity to the first, second and third transistors.

14. A current mirror comprising:

an input node for receiving an input current;

an output node for providing an output current;

first, second, third, and fourth transistors, each transistor comprising first and second current path terminals and a control terminal, the control terminals of the first and second transistors being connected to each other, the first current path terminal of the first transistor and one of the current path terminals of the second transistor being connected to a power supply, the control terminals of the third and fourth transistor being connected to the input node, one of the first and second current path terminals of the third transistor being connected to the output node and the other of the first and second current path terminals of the third transistor being connected to the other of the first and second current path terminals of the second transistor, the first current path terminal of the fourth transistor being connected to the second current path terminal of the first transistor; and

a resistive element arranged between the input node and the second current path terminal of the fourth transistor, the control terminals of the first and second transistors being connected to a node between the resistive element and the second current path terminal of said fourth transistor, said resistive element being a transistor of the opposite polarity to the first, second, third, and fourth transistors.