Differential signal detection circuit

• US 6,194,965 B1
• Filed: 09/03/1999
• Issued: 02/27/2001
• Est. Priority Date: 09/03/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Kruczkowski, Phil, Williams, Bertrand J.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US09/390,591
• Time in Patent Office: 543 Days
• Field of Search: 327/124, 327/307, 330/9, 330/69, 330/258
• US Class Current: 330/258
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first detected data signal in response to (i) one or more first voltages, (ii) one or more second voltages, and (iii) a first reference voltage having a first common mode offset. The second circuit may be configured to present a second detected data signal in response to (i) said one or more first voltages, (ii) said one or more second voltages, and (iii) a second reference voltage having a second common mode offset.

Claims

1. An apparatus comprising:

a first circuit configured to present a first detected data signal in response to (i) one or more first voltages, (ii) one or more second voltages, and (iii) a first reference voltage having a first common mode offset;

a second circuit configured to present a second detected data signal in response to (i) said one or more first voltages, (ii) said one or more second voltages, and (iii) a second reference voltage having a second common mode offset; and

one or more resistors implemented between one or more differential pairs and one or more current sources, said resistors configured to set a voltage threshold trip level to either said first circuit or said second.

2. The apparatus according to claim 1, wherein a first one or more of said resistors present a first voltage threshold trip level to said first circuit and a second one or more of said resistors present a second voltage threshold trip level to said second circuit.

3. The apparatus according to claim 1, further configured to detect valid data on any phase combination of said one or more first voltages and said one or more second voltages.

4. The apparatus according to claim 1, wherein said one or more differential pairs are implemented using MOSFET devices or Bipolar devices.

5. The apparatus according to claim 1, wherein said one or more resistors are implemented using MOSFET devices or Bipolar devices.

6. The apparatus according to claim 1, wherein said first and second circuits comprise voltage comparators configured to detect a serial differential data signal by comparing to a dynamically adjusted threshold limit.

7. The apparatus according to claim 6, wherein said dynamically adjusted threshold limit is generated in response to common mode voltage of said serial differential data stream.

8. A circuit comprising:

means for generating a first detected data signal in response to (i) one or more first voltages, (ii) one or more second voltages, and (iii) a first reference voltage having a first common mode offset;

means for generating a second detected data signal in response to (i) said one or more first voltages, (ii) said one or more second voltages, and (iii) a second reference voltage having a second common mode offset; and

one or more resistors implemented between one or more differential pairs and one or more current sources, said resistors configured to set a voltage threshold trip level to either said means for generating said first detected data signal or said means for generating said second detected data signal.

9. A method for differentially detecting a signal comprising the steps of:

(A) generating a first detected data signal by comparing (i) one or more first voltages, (ii) one or more second voltages, and (iii) a first reference voltage having a first common mode offset; and

(B) generating a s econd detected data signal by comparing (i) said one or more first voltages, (ii) said one or more second voltages, and (iii) a second reference voltage having a second common mode offset; and

(C) generating a resistance to set a voltage threshold trip level presented to steps (A) or (B).

10. The method according to claim 9, wherein step (C) further comprising the sub-steps of:

(C-1) generating a first resistance to set a first voltage threshold trip level presented to step (A); and

(C-2) generating a second resistance to set a second voltage threshold trip level presented to step B.

11. The method according to claim 10 wherein said resistance is generated with active MOSFET devices or Bipolar devices.

12. A method according to claim 11 wherein steps (A) and (B) detects valid serial differential data determined by a comparison to a dynamically adjusted threshold limit.

13. The method according to claim 12, wherein said dynamically adjusted threshold limit is generated in response to common mode voltage of a serial differential data stream.