Method and apparatus for phase shifting a controlled oscillator and applications thereof

• US 6,194,971 B1
• Filed: 04/21/1997
• Issued: 02/27/2001
• Est. Priority Date: 04/21/1997
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Glen, David Ian James, Chau, Ray, Swan, Philip Lawrence, Chow, Hugh Hin-Poon
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US08/840,568
• Time in Patent Office: 1,408 Days
• Field of Search: 331/1.A, 331/20, 331/57, 331/45, 331/34, 331/74, 331/49, 345/213, 327/156, 348/554
• US Class Current: 331/57
• CPC Class Codes: H03B 27/00 Generation of oscillations providing a plurality of outputs of the same frequency but differing in phase, other than merely two anti-phase outputs
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A method and apparatus for providing very small changes in the output oscillation of a controlled oscillation circuit, which may be used in a phase locked loop circuit, is accomplished by a phase-shifting controlled oscillator that includes an oscillation circuit and a selection circuit. The oscillation circuit generates a plurality of oscillations that are of approximately the same frequency and are approximately equally phase shifted from one another. The selection circuit is operably coupled to receive the plurality of oscillations and selects one of them to be the output oscillation based on a control signal. The very small change in the output oscillation occurs when the selection circuit, based on the control signal, selects another one of the oscillations to be the output oscillation. When the change happens, a single pulse is stretched by the phase difference between the “old” output oscillation and the “new” output oscillation.

Claims

1. A phase-shifting controlled oscillator comprising:

an oscillation circuit that generates a plurality of oscillations, wherein the plurality of oscillations are of an approximately identical frequency and are approximately equally phase shifted, and wherein the approximately identical frequency is based on an input control signal; and

a selection circuit operably coupled to receive the plurality of oscillations from the oscillation circuit, wherein the selection circuit provides one of the plurality of oscillations as an output oscillations based on a control signal that is derived from a change rate signal and at least one of the plurality of oscillations, wherein the change rate signal is active when an image update rate does not match a display update rate.

2. The phase-shifting controlled oscillator of claim 1 further comprises, within the oscillation circuit, a plurality of oscillators inter-operably coupled to generate the plurality of oscillations.

3. The phase-shifting controlled oscillator of claim 1 further comprises, within the selection circuit, a multiplexor operably coupled to receive the plurality of oscillations and the control signal.

4. A phase-shifting controlled oscillator comprising:

a ring generator that includes a plurality of inverters cascaded together, wherein the plurality of inverters are operably coupled to receive an input control signal that establishes a frequency of the ring generator, and wherein at least some interconnections between the plurality of inverters provide a plurality of oscillations;

control logic circuit operably coupled to the ring generator and operably coupled to receive a change rate signal, wherein the control logic circuit generates a control signal based on the change rate signal and the plurality of oscillations, wherein the change rate signal is active when an image update rate does not match a display update rate; and

multiplexor operably coupled to receive the plurality of oscillations and to receive the control signal, wherein the multiplexor provides one of the plurality of oscillations as an output oscillation based on the control signal.

5. The phase-shifting controlled oscillator of claim 4 further comprises, within the multiplexor, a plurality of functional switches, wherein each of the plurality of functional switches is coupled to receive a corresponding one of the plurality of oscillations, and wherein one of the plurality of functional switches is activated by the control signal to provide the output oscillation.

6. The phase-shifting controlled oscillator of claim 4 further comprises, within the multiplexor, a plurality of AND gates and an OR gate, wherein each of the plurality of AND gates has as inputs, one of the plurality of oscillations and the control signal, and wherein each output of the plurality of AND gates provides inputs to the OR gate.

7. The phase-shifting controlled oscillator of claim 4 further comprises, within the ring generator, five inverters cascaded together, wherein the input control signal is received by a slew rate control input of each of the plurality of inverters.

8. The phase-shifting controlled oscillator of claim 4 further comprises, within the control logic circuit:

a plurality of flip-flops inter-operably coupled to provide the control signal;

a one-shot enable circuit operably coupled to the plurality of flip-flops and to receive the change rate signal, wherein the one-shot provides an enable signal to the plurality of flip-flops such that the flip-flops change the control signal; and

clock circuit operably coupled to the plurality of flip-flops, wherein the clock circuit provides a clock signal to the plurality of flip-flops based on the output oscillation.

9. A Phase Locked Loop comprising:

a first signal adjust stage operably coupled to receive a reference signal, wherein the first signal adjust stage provides a first signal which has a frequency that is representative of a multiple of a given frequency of the reference signal;

a phase detector operably coupled to receive the first signal and a feedback signal, wherein the phase detector produces from the first signal and the feedback signal a phase signal;

a frequency to voltage circuit operably coupled to receive the phase signal and produce a voltage representation thereof;

a voltage controlled oscillator operably coupled to receive the voltage representation and to produce, therefrom, an output oscillation, the voltage controlled oscillator includes;

an oscillation circuit that generates a plurality of oscillations, wherein the plurality of oscillations are of an approximately identical frequency and are approximately equally phase shifted, and wherein the approximately identical frequency is based on the voltage representation;

control logic circuit operably coupled to the oscillation circuit and operably coupled to receive a change rate signal, wherein the control logic circuit generates a control signal based on the change rate signal and the plurality of oscillations; and

a selection circuit operably coupled to receive the plurality of oscillations from the oscillation circuit, wherein the selection circuit provides, based on the control signal, one of the plurality of oscillations as the output oscillation; and

a second signal adjust stage operably coupled to receive the output oscillation and to produce, therefrom, the feedback signal.

10. The Phase Locked Loop of claim 9 further comprises, within the first signal adjust stage, a divider circuit that divides, by a factor of M, the given frequency of the reference signal.

11. The Phase Locked Loop of claim 10 further comprises, within the second signal adjust stage, a divider circuit that divides, by a factor of N, the output oscillation such that the output oscillation is a function of M,N, and the reference signal.

12. A video graphics circuit comprising:

an update rate difference detection circuit operably coupled to receive an image update rate and a display update rate and to produce, therefrom, a control signal;

a display controller operably coupled to receive a horizontal line total signal, a vertical line total signal, and an output oscillation and to produce, therefrom, the display update rate; and

a Phase Locked Loop operably coupled to provide the output oscillation, the Phase Locked Loop includes;

a first signal adjust stage operably coupled to receive a reference signal, wherein the first signal adjust stage provides a first signal which has a frequency that is representative of a multiple of a given frequency of the reference signal;

a phase detector operably coupled to receive the first signal and a feedback signal, wherein the phase detector produces a phase signal from the first signal and the feedback signal;

a frequency to voltage circuit operably coupled to receive the phase signal and produce a voltage representation thereof;

a voltage controlled oscillator operably coupled to receive the voltage representation and to produce, therefrom, an output oscillation, the voltage controlled oscillator includes;

an oscillation circuit that generates a plurality of oscillations, wherein the plurality of oscillations are of an approximately identical frequency and are approximately equally phase shifted, and wherein the approximately identical frequency is based on the voltage representation;

control logic circuit operably coupled to the oscillation circuit and operably coupled to receive a change rate signal, wherein the control logic circuit generates a control signal based on the change rate signal and the plurality of oscillations; and

a selection circuit operably coupled to receive the plurality of oscillations from the oscillation circuit, wherein the selection circuit provides, based on the control signal, one of the plurality of oscillations as the output oscillation; and

a second signal adjust stage operably coupled to receive the output oscillation and to produce, therefrom, the feedback signal.

13. The video graphics circuit of claim 12 further comprises, within the update rate difference detection circuit, a rate change detector that, based on differences between the image update rate and the display update rate, generates the change rate signal.

14. The video graphics circuit of claim 12 further comprises a display driver operably coupled to the display controller, wherein the display driver provides pixel information to a display.

15. A method for processing video graphic data comprising the steps of:

a) receiving a change rate signal, wherein the change rate signal is used to maintain negligible differences between an image update rate and a display update rate;

b) receiving a horizontal line total signal, a vertical line total signal, and an output oscillation;

c) generating the display update rate from the horizontal line total signal, the vertical line total signal, and the output oscillation;

e) generating a plurality of oscillations; and

f) selecting the output oscillation from the plurality of oscillations based on the change rate signal.

16. The method of claim 15 further comprises, within the generating the plurality of oscillations step, the steps of:

i) adjusting frequency of a reference signal by a first multiplier to produce a first signal which has a frequency that is representative of the multiplier and the frequency of the reference signal;

ii) comparing phase of the first signal and phase of a feedback signal to produce a phase signal;

iii) converting frequency of the phase signal to a voltage signal; and

iv) generating the plurality of oscillations based on the voltage signal, wherein the plurality of oscillations are of an approximately identical frequency and are approximately equally phase shifted.

17. A circuit for processing video data comprising:

rate change detector that produces a change rate signal, wherein the change rate signal is generated, and subsequently used, to maintain negligible differences between an image update rate and a display update rate;

display update rate generator that generates a display update rate from a horizontal line total signal, a vertical line total signal, and an output oscillation; and

output oscillator that produces a plurality of oscillations and selects one of the plurality of oscillations as the output oscillation based on the change rate signal.

18. The circuit of claim 17 further comprises, within the output oscillator:

oscillations generator operably coupled to receive a reference signal and to produce, therefrom, the plurality of oscillations, wherein the plurality of oscillations are of an approximately identical frequency and are approximately equally phase shifted;

control logic circuit operably coupled to the oscillations generator and operably coupled to receive the change rate signal, wherein the control logic circuit generates a control signal based on the change rate signal and the plurality of oscillations; and

selection circuit operably coupled to receive the control signal and select, based on the control signal, the one of the plurality of oscillations.