Inductance device

• US 6,194,987 B1
• Filed: 03/23/1999
• Issued: 02/27/2001
• Est. Priority Date: 03/24/1998
• Status: Expired due to Term

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Lewin, Per Thomas, Zhou, Shu-Ang
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): NGUYEN, TUYEN T
• Application Number:
  US09/274,326
• Time in Patent Office: 707 Days
• Field of Search: 336/200, 336/232, 336/223, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 27/346 Preventing or reducing leakage fields using magnetic shields H01F27/36; using auxiliary windings H01F27/38
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/165 incorporating printed inductors

Abstract

An inductance device has first and second terminals and two conductors. Each conductor forms a loop between the terminals such that a current provided to the first terminal is divided between the conductors. Each current generates a magnetic field. The conductors are disposed such that the combined magnetic field generated by the conductor currents in a space between the conductors is greater than the magnetic field generated by each of the conductors in that space.

Claims

1. An inductance device, comprising:

a first terminal and a second terminal, and

at least two conductors, each conductor forming a loop between the terminals such that a current provided to the first terminal is divided between the conductors, each current generating a magnetic field;

wherein the conductors are disposed such that a combined magnetic field generated by the conductors in a space between the conductors is greater than the magnetic field generated by each of the conductors in the space between the conductors.

2. The inductance device of claim 1, wherein the conductors are elongated planar conductors.

3. The inductance device of claim 1, wherein the conductors are disposed alongside each other.

4. The inductance device of claim 1, wherein at least one of the conductors is arranged to cross over itself at least once.

5. The inductance device of claim 4, wherein the crossing-over conductor is arranged such that is forms a twisted loop.

6. The inductance device of claim 1, wherein the conductors are adjacent, and the currents in the adjacent conductors flow in opposite directions.

7. The inductance device of claim 1, comprising more than two conductor loops.

8. The inductance device of claim 7, wherein the conductors are adjacent and are coupled such that magnetic fields generated by the conductors are superimposed in a space between two adjacent conductors to produce a superimposed magnetic field that is greater than the magnetic field generated by each individual conductor.

9. The inductance device of claim 1, wherein the first and the second terminals are disposed close to each other.

10. A micro-electronic circuit, comprising an inductance device according to claim 1.

11. An integrated circuit substrate, comprising an inductance device according to claim 1.

12. The integrated circuit substrate of claim 11, comprising a plurality of conductor layers, wherein at least one of the loop conductors employs at least two of the conductor layers along a portion of its length;

the layers being interconnected by a plurality of via connections.

13. An inductance device, comprising:

a first terminal and a second terminal; and

two conductors, each conductor forming a loop between the terminals;

wherein the conductors are coupled to the terminals such that a current provided to the first terminal is divided between the conductors, and the conductors are disposed such that, along a major part of each loop, a direction of current in a stretch of one conductor is anti-parallel to the direction of current in an adjacent stretch of the other conductor.