Graphics system with multiported pixel buffers for accelerated pixel processing

• US 6,195,106 B1
• Filed: 01/06/2000
• Issued: 02/27/2001
• Est. Priority Date: 05/03/1994
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Schlapp, Stephen A., Deering, Michael F., Lavelle, Michael G.
• Primary Examiner(s): Chauhan, Ulka J.
• Application Number:
  US09/479,398
• Time in Patent Office: 418 Days
• Field of Search: 345/501-506, 345/520, 345/521, 345/522, 345/519, 345/507, 345/509, 345/515, 345/513, 345/524, 345/518
• US Class Current: 345/545
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.

Claims

1. A frame buffer memory, comprising:

a plurality of memory banks configured to store pixel data that is displayable to form an image on a display device;

one or more video buffers, wherein each video buffer is coupled to two or more of said plurality of memory banks;

a selection unit configured to select one of said video buffers for output to an external video bus;

a pixel buffer coupled to said plurality of memory banks; and

a pixel ALU coupled to receive pixel data from said pixel buffer and from an external rendering bus, wherein said pixel ALU is configured to perform a pixel processing function on the pixel data, wherein said memory banks, said video buffers, said selection unit, said pixel buffer, and said pixel ALU are all part of a single chip.

2. The frame buffer memory as recited in claim 1, wherein said pixel ALU is configured to read a first set of pixel data from the pixel buffer and a second set of pixel data from the rendering bus, and wherein said pixel ALU is configured to blend said first and second sets of pixel data.

3. The frame buffer memory as recited in claim 1, wherein said pixel ALU is configured to read a first set of pixel data from the pixel buffer and a second set of pixel data from the rendering bus, and wherein said pixel ALU is configured to perform a z compare on said first and second sets of pixel data.

4. The frame buffer memory as recited in claim 1, further comprising bus interface logic coupled between said pixel ALU and said rendering bus, wherein said rendering bus is bi-directional.

5. The frame buffer memory as recited in claim 1, wherein each memory bank includes a page buffer.

6. The frame buffer memory as recited in claim 1, wherein said pixel ALU includes circuitry for generating a compare result by performing a compare function on the pixel data, wherein said frame buffer memory further comprises an output data pin for outputting said compare result.

7. The frame buffer memory as recited in claim 6, wherein said frame buffer memory further comprises an input data pin for receiving additional compare results from other frame buffer memories.

8. A graphics system comprising one or more graphics processors configured to receive graphics data and render pixel data into a frame buffer, wherein said frame buffer includes a plurality of frame buffer memory chips, wherein each frame buffer memory chip comprises:

a plurality of memory banks configured to store pixel data that is displayable to form an image on a display device;

one or more video buffers, wherein each video buffer is coupled to two or more of said plurality of memory banks;

a selection unit configured to select one of said video buffers for output to an external video bus;

a pixel buffer coupled to said plurality of memory banks; and

a pixel ALU coupled to receive pixel data from said pixel buffer and from an external rendering bus, wherein said pixel ALU is configured to perform a pixel processing function on the pixel data, wherein said memory banks, said video buffers, said selection unit, said pixel buffer, and said pixel ALU are all part of a single chip.

9. The graphics system as recited in claim 8, wherein the pixel buffers of each frame buffer memory chip collectively form a level one pixel cache.

10. The graphics system as recited in claim 8, wherein each memory bank comprises a page buffer, and wherein the page buffers of each frame buffer memory chip collectively form a level two pixel cache.

11. The graphics system as recited in claim 8, wherein the buffer memory chips are horizontally interleaved.

12. The graphics system as recited in claim 8, wherein said pixel ALUs include circuitry for generating a compare result by performing a compare function on the pixel data, wherein said frame buffer memory further comprises an output data pin for outputting said compare result.

13. The graphics system as recited in claim 12, wherein said frame buffer memory further comprises an input data pin for receiving additional compare results from other frame buffer memories.

14. The frame buffer memory as recited in claim 8, further comprising:

circuitry coupled to receive a compare result input through an input data pin of the frame buffer memory device; and

circuitry for generating a pixel buffer write enable signal by combining the compare result input with the compare result, wherein the pixel buffer write enable signal enables a write of the pixel value into the pixel cache.

15. The frame buffer memory as recited in claim 14 further comprising a pack hit circuit that records pixel updates by setting a hit status bit in response to the pixel buffer write enable signal enables a write of the pixel value into the pixel cache.

16. A method for operating a frame buffer, the method comprising:

receiving new pixel data and instruction information in a frame buffer memory chip;

reading corresponding old pixel data from an on-chip pixel buffer by first transferring the corresponding old pixel data from one of a plurality of on-chip memory banks to the pixel buffer;

using an on-chip ALU to perform a pixel processing function on said pixel data and the corresponding old pixel data;

storing results from the pixel processing function into the pixel buffer and one of the plurality of memory banks;

selecting a subset of the plurality of memory banks;

copying at least a portion of the contents from the selected subset of memory banks to an on-chip video buffer; and

outputting the contents of the video buffer.

17. The method as recited in claim 16, further comprising:

copying a portion of the contents from each memory bank to an on-chip page buffer; and

copying at least a portion of the contents of each page buffer to the video buffer.

18. The method as recited in claim 16, further comprising horizontally interleaving a plurality of frame buffer memory chips.

19. A method for accessing pixel data in a computer graphics system comprising:

receiving a pixel value in a frame buffer memory chip, using an on-chip ALU to perform a pixel processing function on the pixel value, and then transferring the pixel value into a level one on-chip pixel cache;

transferring the pixel value from the level one on-chip pixel cache to an on-chip memory array within a particular on-chip memory bank that buffers a set of pixel data defining an image for display on a display device.

20. The method as recited in claim 19, wherein transferring the pixel value from the level one pixel cache to the memory array comprises:

transferring the pixel value from the level one pixel cache to a level two pixel cache;

writing the pixel value from the level two pixel cache into a set of memory cells of the memory array.

21. The method as recited in claim 20, wherein transferring the pixel value from the level one pixel cache to the level two pixel cache comprises writing each memory cell according to a set of dirty tag bits that correspond to the pixel value.

22. The method as recited in claim 19, wherein performing the pixel processing function on the pixel value comprises:

reading an old pixel value form the level one pixel cache;

generating a new pixel value by combining the old pixel value with the pixel value according to a pixel blending function; and

writing the new pixel value into the level one pixel cache.

23. A computer system, comprising:

a processor coupled to transfer a set of graphics data over a system bus, the graphics data corresponding to an image for display on a display device;

a rendering controller coupled to receive the graphics data over the system bus, the rendering controller coupled to transfer a pixel value over a rendering bus, the pixel value corresponding to the image for the display device; and

a frame buffer memory including;

at least two memory banks for buffering a set of pixel data that defines an image for display on a display device;

a multiple selection unit, wherein said multiple selection unit selects one of said memory banks; and

a pixel ALU coupled to receive a pixel value, the pixel ALU circuit having circuitry for performing a pixel processing function on the pixel value and circuitry for transferring the pixel value into a pixel cache, wherein said memory banks, said pixel cache, and said pixel ALU are each a portion of a single frame buffer memory chip.

24. The computer system as recited in claim 23, wherein the frame buffer memory further comprises:

a pixel cache coupled to access the memory banks.

25. The computer system as recited in claim 24, wherein the pixel ALU of the frame buffer memory comprises a pixel blend circuit coupled to receive an old pixel value from the pixel cache, the pixel blend circuit having circuitry for generating a new pixel value by combining the old pixel value with the pixel value according to the pixel processing function, the pixel blend circuit coupled to store the new pixel value into the pixel cache.

26. The computer system as recited in claim 25, wherein the pixel cache in the frame buffer memory is comprised of a plurality of L1 cache block buffers, wherein the plurality of L1 cache block buffers access the memory banks.

27. The computer system as recited in claim 26, wherein each bank of memory in the frame buffer memory comprises a corresponding page buffer, wherein the page buffers of the at least two banks of memory comprise a L2 pixel cache.

28. The computer system as recited in claim 27, wherein the frame buffer memory further comprises a global bus coupled between the L2 pixel cache and the plurality of L1 cache block buffers, wherein the global bus enables communication between the L1 pixel cache and the L2 pixel cache.

29. The computer system as recited in claim 28, wherein the pixel ALU in the frame buffer memory has circuitry for generating a compare result by performing a compare function between the pixel value and an old pixel value.

30. The computer system as recited in claim 29, wherein the frame buffer memory further comprises circuitry for transferring the compare result over an output data pin of the frame buffer memory device.

31. The computer system as recited in claim 30, wherein the compare function is a magnitude compare function such that the compare result indicates a pass if the pixel value is greater than the old pixel value.

32. The computer system as recited in claim 30, wherein the compare function is a magnitude compare function such that the compare result indicates a pass if the old pixel value is greater than the pixel value.

33. The computer system as recited in claim 30, wherein the compare function is a magnitude compare function such that the compare result indicates a pass if the pixel value does not equal the old pixel value.

34. The computer system as recited in claim 30, wherein the frame buffer memory further comprises:

circuitry coupled to receive a compare result input through an input data pin of the frame buffer memory device; and

circuitry for generating a pixel buffer write enable signal by combining the compare result input with the compare result, wherein the pixel buffer write enable signal enables a write of the pixel value into the pixel cache.

35. The computer system as recited in claim 34, wherein the frame buffer memory further comprises a pack hit circuit that records pixel updates by setting a hit status bit if the pixel buffer write enable signal enables a write of the pixel value into the pixel cache.

36. The computer system as recited in claim 23, wherein the pixel ALU of the frame buffer memory is configured to read the received pixel and blend the received pixel with a newly received pixel.