Feedback driver for memory array bitline

• US 6,195,301 B1
• Filed: 12/21/1999
• Issued: 02/27/2001
• Est. Priority Date: 12/30/1998
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Miller, Rodney D., Schmidt, Eric A., Huffman, James D.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/468,561
• Time in Patent Office: 434 Days
• Field of Search: 365/230.06, 365/189.03, 365/189.04, 365/206, 365/202
• US Class Current: 365/202
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

An auxiliary line driver (514) able to sense data driven on a signal path (502) by a primary line driver (512), and then drive the data on the signal path (502). The auxiliary driver (514) allows a small primary line driver (512) to drive a large load, or a large number of loads (504, 506) without consuming a large area in the region where the primary line driver (512) is fabricated. The auxiliary line driver is particularly useful for driving the memory array of a micromirror device, especially during a block clear operation in which a large number of memory cells (506) are written to simultaneously. When the auxiliary line driver (514) receives an enable signal (518), the auxiliary line driver drives the last input provided to the input of the auxiliary line driver (514).

Claims

1. A memory circuit comprising micromirror device comprising:

an array of memory cells;

at least one bitline electrically connected to at least one of said memory cells;

at least one bitline driver electrically connected to said at least one bitline, said bitline driver for driving a data signal on said bitline connected thereto; and

at least one auxiliary bitline driver electrically connected to said bitline, said auxiliary bitline driver able to sense said data signal and to drive said data signal on said bitline.

2. The memory circuit of claim 1, further comprising a row selector for causing a write operation in at least one said memory cell.

3. The memory circuit of claim 1, said bitline comprising an electrically conductive signal path connected by a middle portion to at least two said memory cells, by a first end portion to said bitline driver, and by a second end portion to said auxiliary driver.

4. The memory circuit of claim 1, said auxiliary driver comprising a tristateable driver circuit, said tristateable driver circuit having an input electrically connected to said bitline and an output electrically connected to said bitline.

5. A line driver circuit comprising:

a load circuit;

a conductive signal path electrically connected to said load circuit;

a line driver electrically connected to said conductive signal path, said line driver for driving a signal on said conductive signal path; and

an auxiliary line driver electrically connected to said conductive path, said auxiliary line driver able to sense said signal and to drive said signal on said conductive path.

6. The line driver circuit of claim 5, further comprising a selector for enabling said load circuit.

7. The line driver circuit of claim 5, said conductive signal path connected by a middle portion to at least two said load circuits, by a first end portion to said line driver, and by a second end portion to said auxiliary line driver.

8. The line driver circuit of claim 5, said auxiliary line driver comprising a tristateable driver circuit, said tristateable driver circuit having an input electrically connected to said conductive signal path and an output electrically connected to said conductive signal path.

9. A method of writing to a memory array, said method comprising the steps of:

driving a data signal on a bitline to a portion of said memory array with a bitline driver;

sensing said data signal at a location remote to said bitline driver;

driving said sensed data signal on said bitline with an auxiliary bitline driver.

10. The method of claim 9, further comprising the step of storing said data signal in at least one memory cell in said memory array.

11. The method of claim 9, said step of driving said data signal on said bitline comprises the step of enabling a first bitline driver.

12. The method of claim 9, said step of sensing said data signal at a location remote to said bitline driver comprising the step of providing said data signal to an input of said auxiliary bitline driver.

13. The method of claim 9, said step of driving said sensed data signal on said bitline with an auxiliary bitline driver comprising the step of enabling an output of said auxiliary bitline driver.