Method and system for hit-less switching
First Claim
1. A system for processing digital signals in a telecommunications system that allows hit-less switching between a first digital signal, in which a first payload, a first payload indicator marker and a first overhead are transported on a first channel, and a second digital signal, in which a second payload identical to the first payload, a second payload indicator marker and a second overhead are transported on a second channel, comprising:
- a first pointer follower to receive the first signal, remove the first overhead, and forward the first payload and the first payload indicator marker;
a second pointer follower to receive the second signal, remove the second overhead, and forward the second payload and the second payload indicator marker;
a first elastic buffer with control circuit to receive the first payload and the first payload indicator marker, to forward the first payload indicator marker, and to forward the first payload;
a second elastic buffer with control circuit to receive the second payload and the second payload indicator marker, to forward the second payload indicator marker, and to forward the second payload;
a monitor circuit to measure a time delay between the first payload indicator marker and the second payload indicator marker and to adjust one of the first or second elastic buffer control circuits by the measured time delay to align the first payload indicator marker and the second payload indicator marker with each other;
a multiplexer to receive the first payload and the second payload, to select between the first payload and the second payload, and to forward a selected payload; and
a pointer generator to receive the selected payload, to generate a third overhead and a third payload indicator, and to include the third overhead and third payload indicator with the selected payload to create a third digital signal with a third payload identical to the first and second payloads.
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Abstract
A system and method are disclosed for processing digital signals in a telecommunications system that allow hit-less switching between a first digital signal in which a first payload, a first payload indicator marker and a first overhead are transported on a first channel, and a second digital signal in which a second payload identical to the first payload, a second payload indicator marker and a second overhead are transported on a second channel. The present invention includes first and second pointer followers, first and second elastic buffers with control circuits, a monitor circuit, a multiplexer, and a pointer generator. The first and second elastic buffer control circuits each further comprise a write counter, a read counter, a phase detector, and a leak-out mechanism for reinitializing the system after a protection switch. The present invention hit-lessly selects between the first and second digital signals without having to frame align the signals.
103 Citations
33 Claims
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1. A system for processing digital signals in a telecommunications system that allows hit-less switching between a first digital signal, in which a first payload, a first payload indicator marker and a first overhead are transported on a first channel, and a second digital signal, in which a second payload identical to the first payload, a second payload indicator marker and a second overhead are transported on a second channel, comprising:
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a first pointer follower to receive the first signal, remove the first overhead, and forward the first payload and the first payload indicator marker;
a second pointer follower to receive the second signal, remove the second overhead, and forward the second payload and the second payload indicator marker;
a first elastic buffer with control circuit to receive the first payload and the first payload indicator marker, to forward the first payload indicator marker, and to forward the first payload;
a second elastic buffer with control circuit to receive the second payload and the second payload indicator marker, to forward the second payload indicator marker, and to forward the second payload;
a monitor circuit to measure a time delay between the first payload indicator marker and the second payload indicator marker and to adjust one of the first or second elastic buffer control circuits by the measured time delay to align the first payload indicator marker and the second payload indicator marker with each other;
a multiplexer to receive the first payload and the second payload, to select between the first payload and the second payload, and to forward a selected payload; and
a pointer generator to receive the selected payload, to generate a third overhead and a third payload indicator, and to include the third overhead and third payload indicator with the selected payload to create a third digital signal with a third payload identical to the first and second payloads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
a first write counter in communication with the first elastic buffer to write the first signal bytes in sequence to the first elastic buffer;
a first read counter in communication with the first elastic buffer to read the first signal bytes in sequence from the first elastic counter; and
a first phase detector to measure the offset between the first write counter and the first read counter and generate a first increment/decrement request signal for the pointer generator; and
wherein the second elastic buffer control circuit further comprises;
a second write counter in communication with the second elastic buffer to write the second signal bytes in sequence to the second elastic buffer;
a second read counter in communication with the second elastic buffer to read the second signal bytes in sequence from the second elastic counter; and
a second phase detector to measure the offset between the second write counter and the second read counter and generate a second increment/decrement request signal for the pointer generator.
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7. The system of claim 6, wherein the monitor circuit adjusts the first read counter by the measured time delay to align the first payload indicator marker with the second payload indicator marker.
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8. The system of claim 6, wherein the monitor circuit adjusts the second read counter by the measured time delay to align the second payload indicator marker with the first payload indicator marker.
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9. The system of claim 6, wherein the first elastic buffer control circuit further comprises a first leaking mechanism to reinitialize the first elastic buffer, and wherein the second elastic buffer control circuit further comprises a second leaking mechanism to reinitialize the second elastic buffer, following a hit-less switch from the first digital signal to the second digital signal, or vice-versa.
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10. The system of claim 9, wherein the first and second elastic buffers operate near their half-full position and wherein the first and second elastic buffers are sized to compensate for at least two times the time delay between the first payload and the second payload during a switch from the first digital signal to the second digital signal, or vice versa.
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11. The system of claim 9, wherein the first elastic buffer operates near its full position and the second elastic buffer operates near its empty position, or vice versa, to be able to compensate for the time delay between the first payload and the second payload during a switch from the first digital signal to the second digital signal, or vice versa.
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12. The system of claim 1, further comprising a receiving unit having a first receiver to receive the first signal and forward it to the first pointer follower and a second receiver to receive the second signal and forward it to the second pointer follower.
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13. The system of claim 1, further comprising:
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a first STS counter communicatively connected to the first pointer follower to track the first overhead frame structure;
a second STS counter communicatively connected to the second pointer follower to track the second overhead frame structure; and
a third STS counter communicatively connected to the pointer generator to track the third overhead frame structure.
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14. The system of claim 1, wherein the first signal is further comprised of a first series of overheads in which a first series of payloads and a first series of payload indicator markers are being transported on a first channel, and wherein the second signal is further comprised of a second series of overheads in which a second series of payloads identical to the first series of payloads and a second series of payload indicator markers are being transported on a second channel.
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15. The system of claim 14, wherein the second series of overheads have payload starting locations, for particular ones of the second series of overheads, that can be different from the starting locations of identical particular payloads in the first series of overheads.
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16. The system of claim 1, wherein the first channel comprises a working channel and the second channel comprises a protect channel.
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17. The system of claim 1, wherein the first and second elastic buffers are sized such that the first payload indicator marker and the second payload indicator marker are located in the first elastic buffer and in the second elastic buffer, respectively, at the same time.
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18. The system of claim 1, wherein the first channel is a first fiber-optic line and the second channel is a second fiber-optic line.
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19. A method for processing digital signals in a telecommunications system that allows hit-less switching between a first digital signal, in which a first payload, a first payload indicator marker and a first overhead are transported on a first channel, and a second digital signal, in which a second payload identical to the first payload, a second payload indicator marker and a second overhead are transported on a second channel, comprising:
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receiving the first signal at a first pointer follower, removing the first overhead, and forwarding the first payload and the first payload indicator marker;
receiving the second signal at a second pointer follower, removing the second overhead, and forwarding the second payload and the second payload indicator marker;
receiving the first payload and the first payload indicator marker at a first elastic buffer with control circuit, forwarding the first payload indicator marker, and forwarding the first payload;
receiving the second payload and the second payload indicator marker at a second elastic buffer with control circuit, forwarding the second payload indicator marker, and forwarding the second payload;
measuring a time delay between the first payload indicator marker and the second payload indicator marker at a monitor circuit and adjusting one of the first or second elastic buffer control circuits by the measured time delay to align the first payload indicator marker and the second payload indicator marker;
receiving the first payload and the second payload at a multiplexer, selecting between the first payload and the second payload, and forwarding a selected payload; and
receiving the selected payload at a pointer generator, generating a third overhead and a third payload indicator, and including the third overhead and third payload indicator with the selected payload to create a third digital signal with a third payload identical to the first and second payloads. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
a first write counter in communication with the first elastic buffer to write the first signal bytes in sequence to the first elastic buffer;
a first read counter in communication with the first elastic buffer to read the first signal bytes in sequence from the first elastic counter; and
a first phase detector to measure the offset between the first write counter and the first read counter and generate a first increment/decrement request signal for the pointer generator to prevent the first elastic buffer from spilling; and
wherein the second elastic buffer control circuit further comprises;
a second write counter in communication with the second elastic buffer to write the second signal bytes in sequence to the second elastic buffer;
a second read counter in communication with the second elastic buffer to read the second signal bytes in sequence from the second elastic counter; and
a second phase detector to measure the offset between the second write counter and the second read counter and generate a second increment/decrement request signal for the pointer generator to prevent the second elastic buffer from spilling.
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25. The method of claim 24 further comprising adjusting the first read counter by the measured time delay with the monitor circuit to align the first payload indicator marker with the second payload indicator marker.
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26. The method of claim 24 further comprising adjusting the second read counter by the measured time delay with the monitor circuit to align the second payload indicator marker with the first payload indicator marker.
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27. The method of claim 19, wherein the first elastic buffer control circuit further comprises a first leaking mechanism to reinitialize the first elastic buffer, and wherein the second elastic buffer control circuit further comprises a second leaking mechanism to reinitialize the second elastic buffer, following a hit-less switch from the first digital signal to the second digital signal, or vice-versa.
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28. The method of claim 27, further comprising the steps of:
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sizing the first and second elastic buffers to compensate for at least two times the time delay between the first payload and the second payload during a switch from the first digital signal to the second digital signal, or vice versa; and
operating the first and second elastic buffers near their half-full position.
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29. The method of claim 27, further comprising the steps of operating the first elastic buffer near its full position and operating the second elastic buffer near its empty position, or vice versa, to be able to compensate for the time delay between the first payload and the second payload during a switch from the first digital signal to the second digital signal, or vice versa.
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30. The method of claim 19, further comprising:
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tracking the first overhead frame structure with a first STS counter communicatively connected to the first pointer follower;
tracking the second overhead frame structure with a second STS counter communicatively connected to the second pointer follower; and
tracking the third overhead frame structure with a third STS counter communicatively connected to the pointer generator.
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31. The method of claim 19, further comprising using the first channel as a working channel and using the second channel as a protect channel.
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32. The method of claim 19, further comprising sizing the first and second elastic buffers such that the first payload indicator marker and the second payload indicator marker are located in the first elastic buffer and in the second elastic buffer, respectively, at the same time.
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33. The method of claim 19, further comprising making the first channel a first fiber-optic line and the second channel a second fiber-optic line.
Specification