Forward-link traffic/paging-channel de-interleaving for communication systems based on closed-form expressions
First Claim
1. A method for de-interleaving a forward-link paging or traffic channel of a communication system, comprising the steps of:
- (a) receiving an interleaved symbol stream for the forward-link channel;
(b) implementing a closed-form expression relating each interleaved symbol position to a corresponding de-interleaved symbol position to generate a de-interleaved symbol position for each symbol in the interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each interleaved symbol position to generate bits in a binary value representing a corresponding de-interleaved symbol position; and
(c) generating a de-interleaved symbol stream from the interleaved symbol stream using the de-interleaved symbol positions.
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Abstract
De-interleaving of forward-link paging or traffic channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For each cdmaOne forward-link paging or traffic channel, the closed-form expression relates each interleaved symbol position to a corresponding de-interleaved symbol position, which is used to generate a de-interleaved symbol stream from the interleaved symbol stream. In one hardware implementation, the forward-link de-interleaver of the present invention has an address generation unit made from two modulo counters.
15 Citations
21 Claims
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1. A method for de-interleaving a forward-link paging or traffic channel of a communication system, comprising the steps of:
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(a) receiving an interleaved symbol stream for the forward-link channel;
(b) implementing a closed-form expression relating each interleaved symbol position to a corresponding de-interleaved symbol position to generate a de-interleaved symbol position for each symbol in the interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each interleaved symbol position to generate bits in a binary value representing a corresponding de-interleaved symbol position; and
(c) generating a de-interleaved symbol stream from the interleaved symbol stream using the de-interleaved symbol positions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 19)
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3. The method of claim 2, wherein the closed-form expression is implemented in software.
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4. The method of claim 2, wherein the closed-form expression is implemented in hardware.
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5. The method of claim 4, wherein the closed-form expression is implemented in a single integrated circuit.
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6. The method of claim 5, wherein the hardware implementation comprises:
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(1) a modulo-6 counter adapted to generate the 3-tuple (t2,t1,t0) from the interleaved symbol position to generate the most significant bits of the de-interleaved symbol position; and
(2) a modulo-64 or higher counter adapted to generate the 6-tuple (q5,q4,q3,q2,q1,q0) based on the carry bit from the modulo-6 counter.
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7. The method of claim 6, wherein the modulo-64 or higher counter generates the 6-tuple (q5,q4,q3,q2,q1,q0) based on the carry bit from the modulo-6 counter and the interleaved symbol position.
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19. The method of claim 1, wherein the closed-form expression is implementable without relying on any lookup tables.
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8. A de-interleaver for de-interleaving a forward-link paging or traffic channel of a communication system, comprising:
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(a) means for receiving an interleaved symbol stream for the forward-link channel;
(b) means for implementing a closed-form expression relating each interleaved symbol position to a corresponding de-interleaved symbol position to generate a de-interleaved symbol position for each symbol in the interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each interleaved symbol position to generate bits in a binary value representing a corresponding de-interleaved symbol position; and
(c) means for generating a de-interleaved symbol stream from the interleaved symbol stream using the de-interleaved symbol positions. - View Dependent Claims (9, 10, 11, 12, 13, 14, 20)
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10. The de-interleaver of claim 9, wherein the closed-form expression is implemented in software.
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11. The de-interleaver of claim 9, wherein the closed-form expression is implemented in hardware.
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12. The de-interleaver of claim 11, wherein the closed-form expression is implemented in a single integrated circuit.
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13. The de-interleaver of claim 12, wherein the hardware implementation comprises:
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(1) a modulo-6 counter adapted to generate the 3-tuple ( t2,t1,t0) from the interleaved symbol position to generate the most significant bits of the de-interleaved symbol position; and
(2) a modulo-64 or higher counter adapted to generate the 6-tuple (q5,q4,q3,q2,q1,q0) based on the carry bit from the modulo-6 counter.
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14. The de-interleaver of claim 13, wherein the modulo-64 or higher counter generates the 6-tuple (q5,q4,q3,q2,q1,q0) based on the carry bit from the modulo-6 counter and the interleaved symbol position.
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20. The de-interleaver of claim 8, wherein the closed-form expression is implementable without relying on any lookup tables.
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15. An integrated circuit having a de-interleaver for de-interleaving a forward-link paging or traffic channel of a communication system, wherein the de-interleaver comprises:
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(A) a symbol buffer; and
(B) an address generation unit adapted to generate symbol addresses for reading interleaved symbols from or writing de-interleaved symbols to the symbol buffer, wherein the address generation unit implements a closed-form expression relating each interleaved symbol position to a corresponding de-interleaved symbol position to generate a de-interleaved symbol position for each symbol in an interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each interleaved symbol position to generate bits in a binary value representing a corresponding de-interleaved symbol position. - View Dependent Claims (16, 17, 18, 21)
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17. The integrated circuit of claim 16, wherein the address generation unit comprises:
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(1) a modulo-6 counter adapted to generate the 3-tuple (t2,t1,t0) from the interleaved symbol position to generate the most significant bits of the de-interleaved symbol position; and
(2) a modulo-64 or higher counter adapted to generate the 6-tuple (q5,q4,q3,q2,q1,q0) based on the carry bit from the modulo-6 counter.
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18. The integrated circuit of claim 17, wherein the modulo-64 or higher counter generates the 6-tuple (q5,q4,q3,q2,q1,q0) based on the carry bit from the modulo-6 counter and the interleaved symbol position.
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21. The integrated circuit of claim 15, wherein the closed-form expression is implementable without relying on any lookup tables.
Specification