Embedded input logic in a high input impedance strobed CMOS differential sense amplifier

• US 6,195,377 B1
• Filed: 02/01/1999
• Issued: 02/27/2001
• Est. Priority Date: 02/01/1999
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Bell, Shane Lewis, Gieseke, Bruce Alan
• Primary Examiner(s): Tran, Toan
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US09/241,212
• Time in Patent Office: 757 Days
• Field of Search: 327/51, 327/52, 327/54, 327/55, 327/57, 327/62, 327/65, 327/112, 365/205, 365/207
• US Class Current: 372/51
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

The present invention provides a sense amplifier that incorporates a logic function. Specifically, that logic function is incorporated into the sense amplifier such that the propagation time of the logic function is avoided and the effective data set-up time of the sense amplifier is reduced. The sense amplifier includes a pair of discharge paths having a true or a complementary version of the logic function associated therewith. When the true or complementary version of the logic function is asserted, one of the discharge paths is turned-on. The output signal that is associated with that discharge path is discharged to a logic low level and the other output signal is pulled to a logic high level. Accordingly, the resulting logic level of the logic function is generated and latched using only the sense amplifier circuit. Therefore, unlike prior art implementations, the data presented to the sense amplifier needs to remain stable for an amount of time that is equivalent to the data set-up timing requirement of the sense amplifier circuit.

Claims

1. A method for imposing a logic function on a plurality of data signals and latching a result of the logic function, the method comprising the steps of:

providing said plurality of data signals to a sense amplifier;

discharging a first internal signal of said sense amplifier through a first discharge path when a first logic circuit, that comprises a portion of said first discharge path, is asserted to impose a first logic function on said plurality of data signals in response to said plurality of data signals developing a first arrangement of logic levels;

generating a representation of said plurality of data signals; and

discharging a second internal signal of said sense amplifier through a second discharge path when a second logic circuit, that comprises a portion of said second discharge path, is asserted to impose a second logic function on said representation of said plurality of data signals in response to said representation of said plurality of data signals.

2. A method for imposing a logic function on a plurality of data signals and latching a result of the logic function, as described in claim 1, further comprising the steps of:

buffering said plurality of data signals in order to generate said representation of said plurality of data signals; and

conveying said representation of said plurality of data signals to said second logic function.

3. A method for latching a result of a logic function, as described in claim 2, wherein said second logic function is a logical inversion of said first logic function such that said second logic function is asserted when said first logic function is de-asserted.

4. A method for latching a result of a logic function, as described in claim 3, wherein said first logic function imposes a logical AND function on said plurality of data signals and said second logic function imposes a logical NAND function on said representation of said plurality of data signals.

5. A method for latching a result of a logic function, as described in claim 3, wherein said first logic function imposes a logical OR function on said plurality of data signals and said second logic function imposes a logical NOR function on said representation of said plurality of data signals.

6. A method for latching a result of a logic function, as described in claim 3, wherein said first logic function imposes a logical XOR function on said plurality of data signals and said second logic function imposes a logical XNOR function on said representation of said plurality of data signals.

7. A method for imposing a logic function on a plurality of data signals and latching a result of the logic function, as described in claim 1, further comprising the steps of:

imposing a third logic function on said plurality of data signals to generate said representation of said plurality of data signals, wherein said third logic function is a logical inversion of said first logic function such that said third logic function is asserted when said first logic function is de-asserted; and

conveying said representation to said second logic function.

8. A method for latching by a sense amplifier, as described in claim 7, wherein said second logic function is asserted in response to said representation of said plurality of data signals being an assertion of said third logic function.

9. A method for latching by a sense amplifier, as described in claim 8, wherein said first logic function imposes a logical AND function on said plurality of data signals and said third logic function imposes a logical NAND function on said plurality of data signals.

10. A method for latching by a sense amplifier, as described in claim 9, wherein said first logic function imposes a logical OR function on said plurality of data signals and said third logic function imposes a logical NOR function on said plurality of data signals.

11. A method for latching by a sense amplifier, as described in claim 8, wherein said first logic function imposes a logical XOR function on said plurality of data signals and said third logic function imposes a logical XNOR function on said plurality of data signals.

12. A method for imposing a logic function on a plurality of data signals and latching a result of the logic function, as described in claim 3, further comprising the steps of:

imposing a third logic function on said plurality of data signals to generate said representation of said plurality of data signals, wherein said representation of said plurality of data signals generated by said third logic function is a logical inversion of said plurality of data signals; and

conveying said representation to said second logic function.

13. A method for internally imposing a logic function on a plurality of data signals and latching a result of the logic function, as described in claim 12 wherein the combination of said second logic function and said third logic function implements a logical inversion of said first logic function such that the combination of said second logic and said third logic function is asserted when said first logic function is de-asserted.

14. A method for internally imposing a logic function on a plurality of data signals and latching a result of the logic function, as described in claim 13, wherein said first logic function imposes a logical AND function on said plurality of data signals and said combination of said second and third logic functions imposes a logical NAND function on said plurality of data signals.

15. A method for internally imposing a logic function on a plurality of data signals and latching a result of the logic function, as described in claim 13, wherein said first logic function imposes a logical OR function on said plurality of data signals and said combination of said second and third logic functions imposes a logical NOR function on said plurality of data signals.

16. A method for internally imposing a logic function on a plurality of data signals and latching a result of the logic function, as described in claim 13, wherein said first logic function imposes a logical XOR function on said plurality of data signals and said combination of said second and third logic functions imposes a logical XNOR function on said plurality of data signals.

17. A method for internally imposing a logic function on a plurality of data signals and

latching a result of the logic function, as described in claim 2, wherein said first logic function is a multiplexer function and said second logic function is a multiplexer function.

18. A computer system, comprising:

a central processing unit connected to a memory system by a system bus;

an I/O system, connected to the system bus by a bus interface device; and

at least one sense amplifier, said sense amplifier comprising;

a first discharge path, coupled to a first internal signal of said sense amplifier, for allowing a charge stored on that first internal signal to be discharged in response to a first logic function being imposed on a number of data signals;

a true logic circuit, implemented within said first discharge path, for imposing said first logic function on said data signals and for conveying said charge to an evaluate unit when imposing said first logic function results in said true logic circuit providing an electrical path from said first internal signal to an evaluate unit; and

said evaluate unit, connecting said true logic circuit to an electrical ground, for conveying said charge, stored on said first internal signal, to said electrical ground when said electrical path is provided.

19. The computer system, as described in claim 18, further comprising:

a second discharge path, coupled to a second internal signal of said sense amplifier, for allowing a charge stored on that second internal signal to be discharged in response to a second logic function being imposed on said data signals;

a complementary logic circuit, implemented within said second discharge path, for imposing said second logic function on a representation of said data signals, said representation generated by a complementing circuit, and for conveying said charge stored on said second internal signal to said evaluate unit when imposing said second logic function results in said complementary logic circuit providing an electrical path from said second internal signal to said evaluate unit; and

said evaluate unit further connecting said complementary logic circuit to said electrical ground, for conveying said charge stored on said second internal signal to said electrical ground.

20. The computer system, as described in claim 19, wherein said complementing logic circuit generates said representation of said data signals by imposing a logically inverted version of said first logic function on said data signals, and said second logic function provides said electrical path in response to a predetermined assertion level of said complementary logic circuit.

21. The computer system, as described in claim 20, wherein said first logic function imposes a logical AND function on said data signals and said complementing logic circuit imposes a logical NAND function on said data signals.

22. The computer system, as described in claim 20, wherein said first logic function imposes a logical OR function on said data signals and said complementing logic function imposes a logical NOR function on said data signals.

23. The computer system, as described in claim 20, wherein said first logic function imposes a logical XOR function on said data signals and said second logic function imposes a logical XNOR function on said data signals.

24. The computer system, as described in claim 19, wherein said first logic function is a multiplexer function and said second logic function is a multiplexer function.

25. The computer system, as described in claim 19, wherein said complementing logic circuit generates said representation of said data signals by buffering said data signals and said second logic function provides said electrical path in response to a logical inversion of said first logic function that is imposed on said data signals.

26. The computer system, as described in claim 25, wherein said first logic function imposes a logical AND function on said data signals, and said second logic function imposes a logical NAND function on said representation of said data signals.

27. The computer system, as described in claim 25, wherein said first logic function imposes a logical OR function on said data signals, and said second logic function imposes a logical NOR function on said representation of said data signals.

28. The computer system, as described in claim 25, wherein said first logic function imposes a logical XOR function on said data signals, and said second logic function imposes a logical XNOR function on said representation of said data signals.

29. The computer system, as described in claim 19, wherein said complementing logic circuit generates said representation of said data signals by inverting said data signals and a combination of said complementing logic circuit and said second logic function implements a logical inversion of said first logic function such that said electrical path is provided in response to a predetermined assertion level of said combination.

30. The computer system, as described in claim 29, wherein said first logic function imposes a logical AND function on said data signals and said combinations of said complementing logic circuit and said second logic function imposes a logical NAND function on said data signals.

31. The computer system, as described in claim 29, wherein said first logic function imposes a logical OR function on said data signals and said combinations of said complementing logic circuit and said second logic function imposes a logical NOR function on said data signals.

32. The computer system, as described in claim 29, wherein said first logic function imposes a logical XOR function on said data signals and said combinations of said complementing logic circuit and said second logic function imposes a logical XNOR function on said data signals.

33. The computer system, as described in claim 19, wherein said true logic circuit comprises a plurality of transistors connected such that said charge stored on said first internal signal is conveyed to said evaluate unit via second electrical path in response to said data signals developing logic levels that would cause a positive assertion of said first logic function.

34. The computer system, as described in claim 33, wherein said complementing logic circuit comprises a plurality of transistors connected such that said charge stored on said first internal signal is conveyed to said evaluate unit via said electrical path in response to said data signals developing logic levels that would cause a negative assertion of said first logic function.

35. A sense amplifier having a reduced set-up timing requirement, comprising:

a first discharge path, coupled to a first internal signal of said sense amplifier, for allowing a charge stored on that first internal signal to be discharged in response to a first logic function being imposed on a number of data signals;

a true logic circuit, implemented within said first discharge path, for imposing said first logic function on said data signals and for conveying said charge to an evaluate unit when said imposition of said first logic function results in said true logic circuit providing a first electrical path from said first internal signal to an evaluate unit; and

said evaluate unit, connecting said true logic circuit to an electrical ground, for conveying said charge, stored on said first internal signal, to said electrical ground when said first electrical path is provided.

36. A sense amplifier, as described in claim 35, further comprising:

a second discharge path, coupled to a second internal signal of said sense amplifier, for allowing a charge stored on that second internal signal to be discharged in response to a second logic function being imposed on said data signals;

a complementary logic circuit, implemented within said second discharge path, for imposing said second logic function on a representation of said data signals, said representation generated by a complementing circuit, and for conveying said charge stored on said second internal signal to said evaluate unit when said imposition of said second logic function results in said complementary logic circuit providing a second electrical path from said second internal signal to said evaluate unit; and

said evaluate unit further connecting said complementary logic circuit to said electrical ground, for conveying said charge stored on said second internal signal to said electrical ground.

37. A sense amplifier, as described in claim 36, wherein said complementing logic circuit generates said representation of said data signals by imposing a logically inverted version of said first logic function on said data signals, and said second logic function provides said electrical path in response to a predetermined assertion level of said complementary logic circuit.

38. A sense amplifier, as described in claim 37, wherein said first logic function imposes a logical AND function on said data signals and said complementing logic circuit imposes a logical NAND function on said data signals.

39. A sense amplifier, as described in claim 37, wherein said first logic function imposes a logical OR function on said data signals and said complementing logic function imposes a logical NOR function on said data signals.

40. A sense amplifier, as described in claim 37, wherein said first logic function imposes a logical XOR function on said data signals and said second logic function imposes a logical XNOR function on said data signals.

41. A sense amplifier, as described in claim 36, wherein said complementing logic circuit generates said representation of said data signals by buffering said data signals and said second logic function provides said electrical path in response to a logical inversion of said first logic function that is imposed on said data signals.

42. A sense amplifier, as described in claim 41, wherein said first logic function imposes a logical AND function on said data signals, and said second logic function imposes a logical NAND function on said representation of said data signals.

43. A sense amplifier, as described in claim 41, wherein said first logic function imposes a logical OR function on said data signals, and said second logic function imposes a logical NOR function on said representation of said data signals.

44. A sense amplifier, as described in claim 41, wherein said first logic function imposes a logical XOR function on said data signals, and said second logic function imposes a logical XNOR function on said representation of said data signals.

45. A sense amplifier, as described in claim 36, wherein said complementing logic circuit generates said representation of said data signals by inverting said data signals and a combination of said complementing logic circuit and said second logic function implements a logical inversion of said first logic function such that said electrical path is provided in response to a predetermined assertion level of said combination.

46. A sense amplifier, as described in claim 45, wherein said first logic function imposes a logical AND function on said data signals and said combinations of said complementing logic circuit and said second logic function imposes a logical NAND function on said data signals.

47. A sense amplifier, as described in claim 45, wherein said first logic function imposes a logical OR function on said data signals and said combinations of said complementing logic circuit and said second logic function imposes a logical NOR function on said data signals.

48. A sense amplifier, as described in claim 45, wherein said first logic function imposes a logical XOR function on said data signals and said combinations of said complementing logic circuit and said second logic function imposes a logical XNOR function on said data signals.

49. A sense amplifier, as described in claim 36, wherein said true logic circuit comprises a plurality of transistors connected such that said charge stored on said first internal signal is conveyed to said evaluate unit via said first electrical path in response to said data signals developing logic levels that cause a positive assertion of said first logic function.

50. A sense amplifier, as described in claim 45, wherein said complementing logic circuit comprises a plurality of transistors connected such that said charge stored on said first internal signal is conveyed to said evaluate unit via said first electrical path in response to said data signals developing logic levels that cause a negative assertion of said first logic function.

51. A sense amplifier having a reduced data set-up timing requirement, comprising:

means for conveying said data signals to a sense amplifier;

means for discharging a first internal signal of said sense amplifier through a first discharge means when a first logic function, that comprises a portion of said first discharge means, is asserted in response to a plurality of data signals developing a first arrangement of logic levels;

means for generating a representation of said plurality of data signals; and

means for discharging a second internal signal of said sense amplifier through a second discharge means when a second logic function, that comprises a portion of said second discharge means, is asserted in response to said representation of said plurality of data signals.

52. A sense amplifier, as described in claim 51, further comprising:

means for buffering said plurality of data signals in order to generate said representation of said plurality of data signals; and

means for conveying said representation of said plurality of data signals to said second logic function.

53. A sense amplifier, as described in claim 52, wherein said second logic function is a logical inversion of said first logic function such that said second logic function is asserted when said first logic function is de-asserted.

54. A sense amplifier, as described in claim 51, further comprising:

means for imposing a third logic function on said plurality of data signals in order to generate said representation of said plurality of data signals, wherein said third logic function is a logical inversion of said first logic function such that said third logic function is asserted when said first logic function is de-asserted; and

means for conveying said representation to said second logic function.

55. A sense amplifier, as described in claim 54, wherein said second logic function is asserted in response to said representation of said plurality of data signals being an assertion of said third logic function.