Method of expanding bus loading capacity

• US 6,195,717 B1
• Filed: 10/01/1997
• Issued: 02/27/2001
• Est. Priority Date: 05/13/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micro Electronics Incorporated
• Inventors: Amdahl, Carlton G., Smith, Dennis H., Agneta, Don, Henderson, Michael G.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Perveen, Rehana
• Application Number:
  US08/942,223
• Time in Patent Office: 1,245 Days
• Field of Search: 395/182.04, 395/821, 395/830, 395/281, 395/652, 395/651, 395/828, 710/101, 710/8, 710/10, 713/1, 713/2
• US Class Current: 710/312
• CPC Class Codes: G06F 1/20 Cooling means
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 11/3089 Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 21/305 by remotely controlling device operation
• CPC Class Codes: G06F 21/31 User authentication
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers
• CPC Class Codes: H04L 12/12 Arrangements for remote connection or disconnection of substations or of equipment thereof
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications
• CPC Class Codes: H04L 41/22 : comprising specially adapted graphical user interfaces [GUI]
• CPC Class Codes: H04L 43/0811 : by checking connectivity
• CPC Class Codes: H04L 67/1001 : for accessing one among a plurality of replicated servers
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method for expanding the loading capacity of a PCI bus in an information processing system having a multiple bus architecture. In one embodiment, the method comprises connecting a processor-to-PCI bridge to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. A plurality of add-in board connectors are coupled to each of the generated PCI buses. In another embodiment, the method comprises connecting two or more processor-to-PCI bridges to a plurality of PCI-to-PCI bridges to generate multiple PCI buses. The resulting system expands the loading capacity of a PCI bus while adding fault-tolerance and resistance to single point failures.

Claims

1. In a computer system having a first, second, and third bus, a method comprising:

connecting a first first-to-second bridge to the first bus;

connecting a second first-to-second bridge to the first bus;

connecting a first set of second-to-third bridges to the first first-to-second bridge via the second bus;

connecting a second set of second-to-third bridges, that are redundant to the first set of second-to-third bridges, to the second first-to-second bridge via the third bus; and

adding a plurality of board connectors redundantly to each of the first and second sets of second-to-third bridges via a plurality of respective buses.

2. The method as defined in claim 1, wherein the act of connecting the first bus includes the act of connecting to a local processor bus.

3. The method as defined in claim 1, wherein the act of connecting via each of the second and third buses includes the act of connecting via a peripheral component interconnect (PCI) bus.

4. The method as defined in claim 1, wherein the act of adding via each of the plurality of respective buses includes the act of adding via a peripheral component interconnect (PCI) bus.

5. The method as defined in claim 1, wherein the act of connecting each of the first and second first-to-second bridges includes the act of connecting a processor-to-PCI bridge.

6. The method as defined in claim 1, wherein the act of connecting each of the second-to-third bridges includes connecting a PCI-to-PCI bridge.

7. The method as defined in claim 1, wherein the act of connecting first set of second-to-third bridges includes connecting four second-to-third bridges.

8. The method as defined in claim 1, wherein the act of connecting second set of second-to-third bridges includes the act of connecting four second-to-third bridges.

9. The method as defined in claim 1, wherein the act of adding the plurality of board connectors includes the act of adding sixteen board connectors.

10. The method as defined in claim 1, wherein the act of adding via each of the plurality of respective buses includes the act of adding via a peripheral component interconnect (PCI) bus.

11. The method as defined in claim 1, wherein the act of adding via each of the plurality of respective buses includes the act of generating each of the plurality of respective buses by a single second-to-third bridge.

27. The method as defined in claim 1, further comprising:

connecting a first-to-fourth bidirectional bridge to the first bus;

connecting a plurality of fourth-to-fifth bi-directional bridges to the first-to-fourth bidirectional bridge via a fourth bus; and

adding a plurality of board connectors to the plurality of fourth-to-fifth bi-directional bridges via a plurality of fifth buses.

28. The method as defined in claim 27, wherein the plurality of third buses are symmetric to the plurality of fifth buses.

12. A program storage device storing instructions that when executed by a computer, having a first, second, and third bus, perform a method comprising:

communicating between a first first-to-second bridge and the first bus;

communicating between a second first-to-second bridge and the first bus;

communicating between a first set of second-to-third bridges and the first first-to-second bridge via the second bus;

communicating between a second set of second-to-third bridges, that are redundant to the first set of second-to-third bridges, and the second first-to-second bridge via the third bus; and

communicating between a plurality of board connectors and each of the first and second sets of second-to-third bridges via a plurality of respective buses, wherein the plurality of board connectors are redundantly connected to the first and second sets of second-to-third bridges.

13. The device as defined in claim 12, wherein the first bus is a local processor bus.

14. The device as defined in claim 12, wherein each of the second and third buses is a peripheral component interconnect (PCI) bus.

15. The device as defined in claim 12, wherein each of the plurality of respective buses is a peripheral component interconnect (PCI) bus.

16. The device as defined in claim 12, wherein each of the first and second first-to-second bridges is a processor-to-PCI bridge.

17. The device as defined in claim 12, wherein each of the second-to-third bridges is a PCI-to-PCI bridge.

18. In a computer system having a first, second, and third bus, a method comprising:

connecting a first bus-to-bus bridge to the first bus to generate the second bus;

connecting a first plurality of bus-to-bus bridges to the second bus;

connecting a second bus-to-bus bridge to the first bus to generate the third bus; and

connecting a second plurality of bus-to-bus bridges to the third bus, wherein the first bus-to-bus bridge and the first plurality of bus-to-bus bridges are redundant to the second bus-to-bus bridge and the second plurality of bus-to-bus bridges.

19. The method as defined in claim 18, wherein the act of connecting the first bus-to-bus bridge and second bus-to-bus bridge includes supporting fault-tolerance functionality.

20. The method as defined in claim 18, wherein the act of connecting the first bus-to-bus bridge fails, the act of connecting the second bus-to-bus bridge remains to maintain connectivity between the first bus and the third bus.

21. The method as defined in claim 18, wherein the act of connecting one of the first plurality of bus-to-bus bridges includes adding a first board, and the act of connecting one of the second plurality of bus-to-bus bridges includes adding a second board.

22. The method as defined in claim 21, wherein the act of adding the first board includes the act of adding a substantially similar second board.

23. The method as defined in claim 21, wherein the acts of adding the first board and second board include the act of connecting the first board and second board to a common device.

29. The device as defined in claim 21, further comprising:

communicating between a first-to-fourth bi-directional bridge and the first bus;

communicating between a plurality of fourth-to-fifth bi-directional bridges and the first-to-fourth bi-directional bridge via a fourth bus; and

communicating between a plurality of board connectors and the plurality of fourth-to-fifth bidirectional bridges via a plurality of fifth buses.

30. The method as defined in claim 29, wherein the plurality of third buses are symmetric to the plurality of fifth buses.

24. In a computer system having a processor bus, a first PCI bus, and a second PCI bus, a method comprising:

connecting a first processor-PCI bridge to the processor bus;

connecting a second processor-PCI bridge to the processor bus;

connecting a first set of four PCI-PCI bridges to the first processor-PCI bridge via the first PCI bus;

connecting a second set of four PCI-PCI bridges to the second processor-PCI bridge via the second PCI bus such that said second set of four PCI-PCI bridges are redundant to the first set of four PCI-PCI bridges; and

redundantly connecting a plurality of board connectors to each of the first and second sets of PCI-PCI bridges via a plurality of respective PCI buses.

25. The method as defined in claim 24, wherein the act of connecting the plurality of board connectors includes the act of connecting sixteen board connectors.

26. The method as defined in claim 24, wherein the act of connecting via the plurality of respective PCI buses includes the act of connecting via four PCI buses.