Process and apparatus for synchronizing the block counter in an RDS radio data receiver

• US 6,195,783 B1
• Filed: 09/19/1997
• Issued: 02/27/2001
• Est. Priority Date: 03/27/1995
• Status: Expired due to Term

• Current Assignee: Blaupunkt-Werke GmbH (Aurelius AG)
• Original Assignee: Blaupunkt-Werke GmbH (Aurelius AG)
• Inventors: Nyenhuis, Detlev, Hegeler, Wilhelm
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): Lamarre, Guy J.
• Application Number:
  US08/913,371
• Time in Patent Office: 1,257 Days
• Field of Search: 714/798, 714/762, 714/763, 714/775, 375/340, 375/357, 375/365, 370/347
• US Class Current: 714/798
• CPC Class Codes: H04H 2201/13 radio data system/radio broadcast data system [RDS/RBDS]
• CPC Class Codes: H04H 40/18 Arrangements characterised by circuits or components specially adapted for receiving
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A process and apparatus for synchronizing the block counter of an RDS radio data receiver is described. According to the process, the bits stored in a 26-bit shift register, are cycled at least n times in said register, n being the number of allowable offset words, and the shift register content is X-OR gated with another offset word in a given sequence for each cycle. The gating result is received by a syndrome detection circuit, which triggers a sync pulse when the zero syndrome is detected, and the sync pulse resets the bit counter to zero and sets the block counter to the address counter status assigned to the offset word in the offset word generator.

Claims

1. A method for synchronizing a block counter in an RDS receiver, comprising the steps of:

consecutively reading in bits from an output of an RDS receiver to a 26-bit shift register, the bits having a bit frequency and being read into the shift register at the bit frequency;

cycling the bits in the shift register during a bit period for transfer into a syndrome detection circuit wherein in each bit period, the bits cycle a number of times at least equal to a number of total allowable offset words and bits are X-OR gated with bits of one of a plurality of offset words generated by an offset word generator, the bits being X-OR gated in a standard sequence controlled by an address counter prior to being transferred into the syndrome detection circuit; and

triggering a sync pulse via the syndrome detection circuit for predetermined cyclically used offset words, the sync pulse being generated when a zero syndrome is detected, the sync pulse setting a block counter to a status of the address counter and resetting a bit counter to zero when the one of the plurality of offset words is a predetermined offset word.

2. The method according to claim 1, wherein the block counter has a block counter status, the block counter status being set to a status of two lowest positions of the address counter, the address counter controlling the generating of the plurality of offset words in the offset word generator.

3. The method according to claim 1, further comprising the step of counting detections of the zero syndrome in a flywheel circuit, and wherein the sync pulse is only triggered if, when a zero syndrome is detected, a number of previous detections of the zero syndrome is less than a predefined number.

4. The method according to claim 3, wherein the number of detections of the zero syndrome is incremented by one if, when the sync pulse occurs, one of correct data and correctable data is stored in the shift register, and the number of detections of the zero syndrome is decremented by one if the sync pulse occurs one of outside a block clock pulse and with an incorrect offset word.

5. A circuit for synchronizing a block counter in an RDS receiver, comprising:

a shift register having a clock input and an output;

an offset word generator having a clock input and an address counter, the address counter having a count input;

a first X-OR element having a first input, a second input, and an output, the first input of the first X-OR element connected to the output of the shift register and the second input of the first X-OR element connected to the offset word generator;

a syndrome detection circuit comprising;

a syndrome register having an input, a clock input and an output, the input of the syndrome register connected to the output of the first X-OR element; and

a first gate circuit having an input, a clock input, and an output, the input of the first gate circuit connected to the syndrome register, the first gate circuit detecting a zero syndrome;

a control unit connected to the clock input of the shift register, to the clock input of the offset word generator, to the clock input of the syndrome register, and to the count input of the address counter, the control unit generating packets of twenty-six cycling pulses for the shift register and the syndrome register a number of times in a bit period equal to a number of allowable offset words plus a freely selectable number, the control unit delivering a number of counting pulses in each bit period equal to the number of allowable offset words; and

a block counter having a block counter status, the block counter connected to the address counter and receiving an address counter status, wherein the syndrome detection circuit compares a syndrome obtained from radio data to a predefined syndrome and, when the syndromes match, triggers a sync pulse.

6. The circuit according to claim 5, wherein the shift register includes a 26-bit shift register and the first gate circuit includes a 10-bit NOR circuit.

7. The circuit according to claim 6, wherein the syndrome register has a plurality of cells, each of the plurality of cells having an output, the outputs of the plurality of cells being combined in the first gate circuit, and the output of the first gate circuit is adapted to pick up the sync pulse.

8. The circuit according to claim 5, wherein the control unit comprises:

a first generator having an output, the first generator generating first generator pulses;

a 4-bit counter having an input and an overflow, the input-of the 4-bit counter connected to the output of the first generator, the 4-bit counter dividing the first generator pulses selectively by one of ten and sixteen;

a 2-bit counter connected to the overflow of the 4-bit counter, the 2-bit counter having a first position, a second position, a third position, and a fourth position; and

a second generator generating second generator pulses;

wherein when the 2-bit counter is in one of the first position and the third position, the 4-bit counter divides the first generator pulses by ten;

wherein when the 2-bit counter is in one of the second position and the fourth position, the 4-bit counter divides the first generator pulses by sixteen;

wherein when the 2-bit counter is in one of the second position and the third position, the output of the first generator is connected via a second gate circuit to the clock input of the shift register, to the clock input of the offset word generator and to the clock input of the syndrome register; and

wherein the second generator pulses reset the 2-bit counter and the 4-bit counter and increment the address counter by one.

9. The circuit according to claim 8, wherein the first generator includes a 456 kHz generator and the second generator includes a 9.5 kHz generator.

10. The circuit according to claim 5, further comprising:

an up/down counter having at least two count inputs, one of the count inputs having an up-AND gate and another of the count inputs having a down-AND gate, each of the up-AND gate and the down-AND gate having a first input and a second input; and

a comparator circuit having an equality output and an inequality output, the comparator circuit comparing the address counter status with the block counter status;

wherein the first input of the up-AND gate and the first input of the down-AND gate are connected to the output of the first gate circuit;

wherein the second input of the up-AND gate is connected to the equality output of the comparator circuit; and

wherein the second input of the down-AND gate is connected to the inequality output of the comparator circuit.

11. The circuit according to claim 10,

wherein the syndrome register has a plurality of cells, each of the cells having an output, the outputs of the plurality of cells being combined in the first gate circuit, and the output of the first gate circuit is able to pick up the sync pulse;

wherein the control unit comprises;

a first generator having an output, the first generator generating first generator pulses;

a 4-bit counter having an input and an overflow, the input of the 4-bit counter connected to the output of the first generator, the 4-bit counter dividing the first generator pulses optionally by ten or sixteen;

a 2-bit counter connected to the overflow of the 4-bit counter, the 2-bit counter having a first position, a second position, a third position, and a fourth position; and

a second generator generating second generator pulses;

wherein when the 2-bit counter is in one of the first position and the third position, the 4-bit counter divides the first generator pulses by ten;

wherein when the 2-bit counter is in one of the second position and the fourth position, the 4-bit counter divides the first generator pulses by sixteen;

wherein when the 2-bit counter is in one of the second position and the third position, the output of the first generator is connected via a second gate circuit to the clock input of the shift register, to the clock input of the offset word generator and to the clock input of the syndrome register; and

wherein the second generator pulses reset the 2-bit counter and the 4-bit counter and increment the address counter by one.