Mapping heterogeneous logic elements in a programmable logic device

• US 6,195,788 B1
• Filed: 10/09/1998
• Issued: 02/27/2001
• Est. Priority Date: 10/17/1997
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Leaver, Andrew, Heile, Francis B.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/169,213
• Time in Patent Office: 872 Days
• Field of Search: 716/1-21
• US Class Current: 716/116
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit is disclosed. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device such as selectively choosing the best combination of product term logic elements and look up table logic elements.

Claims

1. A method of mapping an electronic design to a target hardware device using a plurality of heterogeneous logic elements, the target hardware device including first type logic elements and second type logic elements interconnected by way of programmable connectors, comprising:

(a) forming a first logical region using the first type logic element;

(b) forming a second logical region using the second type logic element, wherein the first logical region and the second logical region perform logically equivalent sub-functions of the electronic design;

(c) comparing the first and the second logical regions;

(d) choosing either the first logical region or the second logical region based upon the comparing (c);

(e) adding the chosen logical region from operation (d) to a final mapping list; and

(f) repeating operations (a)-(e) until the electronic design is fully mapped.

2. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 1, wherein the first type logic element is a PTERM logic elements.

3. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 2 wherein the second type logic element is a look up table (LUT) logic element.

4. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 3, wherein the first logic region is a PTERM logic cone.

5. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 4, wherein the second logic region is a LUT logic cone, wherein the PTERM logic cone and the LUT logic cone perform logically equivalent sub-functions of the electronic design.

6. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 5, wherein the comparing comprises:

(g) calculating a PTERM logic cone'"'"'s cost and an associated LUT logic cone'"'"'s cost;

(h) sorting the PTERM logic cone'"'"'s cost and the associated LUT logic cone'"'"'s cost using a pre-selected cost factor.

7. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 6, wherein the choosing further comprises:

(i) determining if there are available PTERM logic elements;

(j) if it is determined that there are no available PTERM logic elements, then selecting the best of the remaining unchosen LUT logic cones from operation (h); and

(k) if it is determined that there are available PTERM logic elements, then selecting the highest ranked available PTERM logic cone.

8. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 7, wherein the choosing further comprises:

(l) adjusting the cost of overlapping PTERM logic cones or overlapping LUT logic cones.

9. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 1, wherein the target hardware device is a programmable logic device.

10. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 6, wherein the pre-selected cost factor is logic density.

11. A method of mapping an electronic design using heterogeneous logic elements as recited in claim 6, wherein the pre-selected cost factor is speed.

12. A method of mapping an electronic design to a heterogeneous device having first logic elements of a first type and second logic elements of a second type, the method comprising:

mapping the electronic design to conform to the first logic elements and thereby form a first mapping;

mapping the electronic design to conform to the second logic elements and thereby form a second mapping; and

comparing the first and second mappings of a logically equivalent logic region to choose one of these mappings for implementing the logic region on a target hardware device.

13. The method of claim 12, wherein the mapping is performed during compilation of the electronic design.

14. The method of claim 12, further comprising synthesizing the electronic design prior to the mappings.

15. The method of claim 12, further comprising placing the chosen mapping of the logic region on the target hardware device.

16. The method of claim 12, further comprising performing the comparing operation for a plurality of logic regions of the electronic design.

17. The method of claim 12, further comprising defining the logic region prior to comparing the first and second mappings.

18. The method claim 17, wherein defining the logic region comprises:

identifying anchor nodes that are functionally equivalent in both the first and second mappings; and

identifying as said logic region, logic bounded by at least two of said anchor nodes.

19. The method of claim 18, wherein the anchor nodes include at least registers and I/O nodes.

20. The method of claim 12, wherein the first logic elements are PTERM logic elements and wherein the second logic elements are look up table logic elements.

21. An electronic device implementing the electronic design as mapped by the method of claim 12.

22. A programmable logic device implementing the electronic design as mapped by the method of claim 12.

23. A computer program product comprising computer program instructions provided on a computer readable medium, the computer program instructions specifying a method of mapping an electronic design to a heterogeneous device having first logic elements of a first type and second logic elements of a second type, the method comprising:

mapping the electronic design to conform to the first logic elements and thereby form a first mapping;

mapping the electronic design to conform to the second logic elements and thereby form a second mapping; and

comparing the first and second mappings of a logically equivalent logic region to choose one of these mappings for implementing the logic region on a target hardware device.

24. The computer program product of claim 23, wherein the computer program instructions define additional operations for compiling the electronic design.

25. The computer program product of claim 23, wherein the computer program instructions specify defining the logic region prior to comparing the first and second mappings.

26. The computer program product of claim 25, wherein the computer program instructions specify that defining the logic region comprises:

identifying anchor nodes that are functionally equivalent in both the first and second mappings; and

identifying as said logic region, logic bounded by at least two of said anchor nodes.

27. The computer program product of claim 23, wherein the first logic elements are PTERM logic elements and the second logic elements are look up table logic elements.

28. The computer program product of claim 23, wherein the comparing operation involves determining a cost associated with each mapping of the logic region.

29. The computer program product of claim 28, wherein the cost is logic density, speed, or a combination thereof.