Parallel test method

• US 6,196,677 B1
• Filed: 05/20/1998
• Issued: 03/06/2001
• Est. Priority Date: 05/20/1998
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Spano, John D.
• Primary Examiner(s): BROWN, GLENN WARNER
• Application Number:
  US09/082,034
• Time in Patent Office: 1,021 Days
• Field of Search: 324/754, 324/765, 324/73.1
• US Class Current: 351/44
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G06F 11/2273 Test methods

Abstract

The present invention is directed to a method and system for testing a plurality of integrated circuits. According to one embodiment of the invention, a method and system for testing a plurality of integrated circuits using a probe card having a plurality of circuit sites is provided. First, a group of the plurality of integrated circuits is associated with the probe card and a first-pass test is performed in parallel on each associated integrated circuit in the group using a first number of signal channels for each circuit site. A particular one of the integrated circuits in the group which passed the first-pass tests is then selectively associated with a particular one of the circuit sites, and a second-pass test is performed on the particular one integrated circuit using a second number of signal channels greater than the first number. In this manner, the use of test system resources may be optimized with expensive second-pass tests (e.g., performance tests) only being performed on circuits passing less-expensive first-pass tests (e.g., BIST and scan tests).

Claims

1. A method for testing a plurality of integrated circuits using a probe card having a plurality of circuit sites, comprising:

a) associating with the probe card a group of the plurality of integrated circuits;

b) performing a first-pass test in parallel on each associated integrated circuit in the group using a first number of signal channels for each circuit site;

c) selectively associating with a particular one of the circuit sites a particular one of the integrated circuits in the group which passed the first-pass test; and

d) performing a second-pass test on the particular one integrated circuit using a second number of signal channels greater than the first number.

2. The method of claim 1, further including repeating (a)-(b) until all the integrated circuits have been first-pass tested prior to performing the selectively associating step.

3. The method of claim 2, further including repeating steps (c)-(d) for each integrated circuit which passes the first-pass test.

4. The method of claim 3, wherein the steps (c) and (d) are performed only on die that passed the first-pass test.

5. The method of claim 1, wherein the plurality of integrated circuits are die on a wafer.

6. The method of claim 1, wherein the first-pass test includes a sequential chain test.

7. The method of claim 6, wherein the first-pass test includes a built-in self-test.

8. The method of claim 7, wherein the second-pass test is a performance test.

9. The method of claim 1, wherein the first-pass test includes a built-in self-test.

10. The method of claim 9, wherein the second-pass test is a performance test.

11. The method of claim 1, wherein the second-pass test is a performance test.

12. The method of claim 1, wherein the step of performing a second-pass test includes using a first circuit site of the probe card adapted to perform the second-pass circuit test on the particular integrated circuit.

13. The method of claim 12, wherein the first circuit site is adapted to provide a subset of a full complement of first signal channels during the first pass test and is adapted to provide the full complement of the first signal channels during the second pass test.

14. The method of claim 12, wherein the first circuit site is adapted to provide a full complement of first signal channels during the first pass test and is adapted to provide a subset of the full complement of the first signal channels during the second pass test.

15. A method for testing a plurality of integrated circuits using a probe card having a plurality of circuit sites, comprising:

a) associating with the probe card a group of the plurality of integrated circuits;

b) performing a first-pass test in parallel on each associated integrated circuit in the group using a first number of signal channels for each circuit site;

c) repeating (a) and (b) until the first-pass test is performed on all of the integrated circuits;

d) selectively associating with a particular one of the circuit sites a particular one of the integrated circuits in the group which passed the first-pass test;

e) performing a second-pass test on the particular one integrated circuit using a second number of signal channels greater than the first number; and

f) repeating steps (d) and (e) until the second-pass test is performed on each integrated circuit which passed the first-pass test.

16. The method of claim 15, wherein the step of performing a second-pass test includes using a first circuit site of the probe card adapted to perform the second-pass circuit test on each integrated circuit.

17. A testing system for testing a plurality of integrated circuits using a probe card having a plurality of circuit sites, comprising:

a) means for associating with the probe card a group of the plurality of integrated circuits;

b) means for performing a first-pass test in parallel on each associated integrated circuit in the group using a first number of signal channels for each circuit site;

c) means for selectively associating with a particular one of the circuit sites a particular one of the integrated circuits in the group which passed the first-pass test; and

d) means for performing a second-pass test on the particular one integrated circuit using a second number of signal channels greater than the first number.

18. The testing system of claim 17, further including means for repeating (a)-(b) until all the integrated circuits have been first-pass tested prior to performing the selectively associating step.

19. The testing system of claim 18, further including means for repeating (c)-(d) for each integrated circuit which passes the first-pass test.

20. The testing system of claim 18, further including means for performing (c) and (d) only on die that passed the first-pass test.

21. The testing system of claim 20, wherein the first-pass test includes a built-in self-test.

22. The testing system of claim 20, wherein the second-pass test is a performance test.

23. The testing system of claim 17, wherein the second-pass test is a performance test.

24. The testing system of claim 17, wherein said means for performing the second-pass test includes using one of the circuit sites of the probe card to perform the second-pass circuit test on the particular integrated circuit.

25. The testing system of claim 24, wherein the circuit sites of the probe card include a first circuit site adapted to provide a full complement of first signal channels and a second set of circuit sites adapted to provide a subset of the full complement of the first signal channels.

26. The testing system of claim 24, wherein the circuit sites of the probe card include a first circuit site adapted to provide a subset of the full complement of first signal channels during the first pass test and adapted to provide the full complement of the first signal channels during the second pass test.

27. A testing system for parallel testing integrated circuits, comprising:

a probe card having a plurality of circuit sites, each circuit site having a plurality of signal channels;

a chuck for holding a wafer having a plurality of integrated circuits; and

test equipment, coupled to the probe card and chuck, configured to;

associate with the probe card a group of the plurality of integrated circuits;

perform a first-pass test in parallel on each associated integrated circuit in the group using a first number of signal channels for each circuit site;

selectively associate with a particular one of the circuit sites a particular one of the integrated circuits in the group which passed the first-pass test; and

perform a second-pass test on the particular one integrated circuit using a second number of signal channels greater than the first number.