Process for fabricating integrated circuit devices having thin film transistors

• US 6,197,663 B1
• Filed: 12/07/1999
• Issued: 03/06/2001
• Est. Priority Date: 12/07/1999
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Raju, Venkataram Reddy, Katz, Howard Edan, Dodabalapur, Ananth, Chandross, Edwin Arthur
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): ROCCHEGIANI, RENZO
• Application Number:
  US09/456,210
• Time in Patent Office: 455 Days
• Field of Search: 438/455, 438/149, 438/99
• US Class Current: 438/455
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene

Abstract

A process for fabricating an integrated circuit device is disclosed. The integrated circuit has a plurality of TFTs and an electrical interconnect structure. In the process, at least some constituents of the TFTs are formed on a first substrate. At least the interconnect structure is formed on a second substrate. The two substrates are laminated together to form the integrated circuit device having fully formed TFTs.

Claims

1. A process for integrated circuit device fabrication comprising:

forming at least a portion of a thin film transistor on a first flexible substrate;

forming an interconnect structure on a second flexible substrate;

laminating the first flexible substrate to the second flexible substrate, thereby electrically interconnecting the thin film transistor with the interconnect structure.

2. The process of claim 1 wherein the thin film transistor comprises a gate, a gate dielectric, a semiconductor, a source and a drain.

3. The process of claim 2 wherein the entire thin film transistor is formed on the first substrate.

4. The process of claim 2 wherein the gate, gate dielectric and semiconductor of the thin film device are formed on the first substrate and the source and drain of the thin film device are formed on the second substrate.

5. The process of claim 4 wherein the semiconductor is an organic semiconductor.

6. The process of claim 4 wherein the semiconductor is an inorganic semiconductor.