Interconnect structure in a semiconductor device and method of formation

• US 6,197,688 B1
• Filed: 02/12/1998
• Issued: 03/06/2001
• Est. Priority Date: 02/12/1998
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Simpson, Cindy Reidsema
• Primary Examiner(s): Booth, Richard
• Assistant Examiner(s): Kennedy, Jennifer M.
• Application Number:
  US09/022,933
• Time in Patent Office: 1,118 Days
• Field of Search: 438/678, 438/687, 438/629
• US Class Current: 438/678
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a conductive interconnect (38) is formed in a semiconductor device by depositing a dielectric layer (28) on a semiconductor substrate (10). The dielectric layer (28) is then patterned to form an interconnect opening (29). A tantalum nitride barrier layer (30) is then formed within the interconnect opening (29). A catalytic layer (31) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer (30). A layer of electroless copper (32) is then deposited on the catalytic layer (31). A layer of electroplated copper (34) is then formed on the electroless copper layer (32), and the electroless copper layer (32) serves as a seed layer for the electroplated copper layer (34). Portions of the electroplated copper layer (34) are then removed to form a copper interconnect (38) within the interconnect opening (29).

Claims

1. A method for forming an interconnect structure in a semiconductor device comprising the steps of:

providing a semiconductor substrate;

forming a tungsten plug overlying the semiconductor substrate;

forming a dielectric layer overlying the tungsten plug;

removing a portion of the dielectric layer to expose at least a portion of the tungsten plug within an opening;

forming a catalytic layer comprising a palladium-tin alloy within the opening;

forming a conductive seed layer within the opening and overlying the catalytic layer, wherein the conductive seed layer is formed using an electroless plating process; and

forming a conductive metal layer overlying the conductive seed layer, wherein the conductive metal layer is formed using an electroplating process.

2. The method of claim 1, further comprising the step of:

forming a barrier layer within the opening prior to forming the catalytic layer.

3. The method of claim 2, wherein the step of forming the barrier layer is further characterized as forming a barrier layer comprising titanium (Ti).

4. The method of claim 2, wherein the step of forming the barrier layer is further characterized as forming a barrier layer comprising tantalum (Ta).

5. The method of claim 2, wherein the step of forming the barrier layer is further characterized as forming a barrier layer comprising tungsten (W).

6. The method of claim 2, further comprising the step of:

etching the barrier layer prior to forming the catalytic layer.

7. The method of claim 1 wherein the step of forming a conductive metal layer further comprises:

forming a conductive metal layer overlying the conductive seed layer, wherein the conductive metal layer is formed using an electroplating process wherein the opening is aluminum free.

8. A method for forming an interconnect structure in a semiconductor device comprising the steps of:

providing a semiconductor substrate;

forming a tungsten plug over the substrate;

forming a dielectric layer overlying the semiconductor substrate;

forming an opening within the dielectric layer to expose a portion of the tungsten plug;

forming a catalytic layer comprising a palladium-tin alloy within the opening;

forming a first copper layer within the opening using an electroless plating process after forming the catalytic layer;

forming a second copper layer within the opening using an electroplating process, wherein the second copper layer abuts the first copper layer and the first copper layer serves as a seed layer for the electroplating process; and

polishing the second copper layer and the first copper layer to form a conductive interconnect within the opening.

9. The method of claim 8, wherein the step of forming the opening is further characterized as forming a dual inlaid opening.

10. The method of claim 8, further comprising the step of:

forming a condutive barrier layer within the opening to forming the catalytic layer.

11. The method of claim 10, wherein the step of forming the conductive barrier layer is further characterized as forming a barrier layer comprising tantalum (Ta).

12. The method of claim 11, wherein the step of forming the barrier layer comprising tantalum is further characterized as forming a tantalum nitride barrier layer.

13. The method of claim 10, wherein the step of forming the conductive barrier layer is further characterized as forming a titanium nitride barrier layer.

14. A method for forming an interconnect structure in a semiconductor device comprising the steps of:

providing a semiconductor substrate;

forming a doped region within the semiconductor substrate;

forming a tungsten plug over the substrate;

forming a first dielectric layer overlying the semiconductor substrate;

forming a first opening within the first dielectric layer to expose a portion of a tungsten plug;

forming a first conductive barrier layer within the first opening;

forming a first catalytic layer comprising a palladium-tin alloy within the first opening, the first catalytic layer overlying the first conductive barrier layer;

forming a first conductive seed layer within the first opening using an electroless plating process, the first conductive seed layer overlying the first conductive barrier layer; and

forming a first copper layer with the first opening using an electroplating process, the first copper layer overlying the first conductive seed layer;

polishing the first copper layer to form a first conductive interconnect;

forming a second dielectric layer overlying the first conductive interconnect;

forming a second opening in the second dielectric layer to expose a portion of the first conductive interconnect;

forming a second conductive barrier layer within the second opening;

forming a second catalytic layer comprising a palladium-tin alloy within the second opening, the second catalytic layer overlying the second conductive barrier layer;

forming a second conductive seed layer within the second opening using an electroless plating process, the second conductive seed layer overlying the second conductive barrier layer;

forming a second copper layer within the second opening using an electroplating process, the second copper layer overlying the second conductive seed layer; and

polishing the second copper layer to form a second conductive interconnect.

15. The method of claim 14, wherein the step of polishing the first copper layer is further characterized as polishing the first copper layer to form a first conductive interconnect adjacent to the doped region, wherein the first conductive interconnect is electrically shorted to the doped region.