Semiconductor device and method for manufacturing the same

• US 6,198,130 B1
• Filed: 01/06/1998
• Issued: 03/06/2001
• Est. Priority Date: 08/04/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nobuto, Shinji, Takahashi, Hideki, Watabe, Kiyoto
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): Hu, Shouxiang
• Application Number:
  US09/003,338
• Time in Patent Office: 1,155 Days
• Field of Search: 257/328, 257/329, 257/331, 257/332, 257/341, 257/342, 257/343, 257/335, 257/162, 257/172, 257/347, 257/409
• US Class Current: 257/343
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

An ON-state voltage is reduced. A line of gate trenches 8 is formed on an n-type silicon layer (a SOI layer) 3 so as to divide a p-type base layer 4 and an n-type emitter layer 5. The gate trench 8 extends from the n-type emitter layer 5 toward a collector electrode 21. A gate electrode 10 is buried in the gate trench 8 with a gate insulation film 9 interposed therebetween. The gate electrode 10 is provided opposite to a vertical section of the p-type base layer 4. Therefore, a channel width can be kept great. Furthermore, a wide region of the n-type silicon layer 3 which is provided opposite to the gate trench 8 functions as an accumulation layer of a hole. As a result, the ON-state voltage can be reduced.

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type having a first principal surface and a second principal surface;

a second semiconductor layer of a second conductivity type which is selectively formed on said first principal surface of said first semiconductor layer;

a third semiconductor layer of a first conductivity type selectively formed on an inside of an exposed surface of said second semiconductor layer, wherein said third semiconductor layer is shallower than said second semiconductor layer, has a higher impurity concentration than that of said first semiconductor layer, and said third semiconductor layer is formed between a first edge and a second edge of said second semiconductor layer, said first and second edges being adjacent to said first semiconductor layer;

a fourth semiconductor layer which is selectively exposed to said first principal surface of said first semiconductor layer apart from said second semiconductor layer;

a first main electrode connected to said second and third semiconductor layers;

a second main electrode connected to said fourth semiconductor layer;

a gate trench defined by said first semiconductor layer, said gate trench being open to said first principal surface, said gate trench extending in a direction orthogonal to a longitudinal direction of said second semiconductor layer, extending in said first semiconductor layer across said first edge of said second semiconductor layer, extending in said first semiconductor layer across said second edge of said second semiconductor layer, and said gate trench being deeper than said second semiconductor layer;

a gate insulation film covering an internal wall of said gate trench; and

a gate electrode buried in said gate trench with said gate insulation film interposed therebetween.

2. The semiconductor device according to claim 1, wherein said gate trench is divided into lines of unit gate trenches arranged at regular intervals, and

a connecting portion of said first main electrode and said second and third semiconductor layers is divided into a plurality of regions interposed between said lines of said unit gate trenches.

3. The semiconductor device according to claim 2, wherein said fourth semiconductor layer is a semiconductor layer of a second conductivity type, and

said connecting portion is provided thinly in a part of said regions.

4. The semiconductor device according to claim 2, wherein said fourth semiconductor layer is a semiconductor layer of a second conductivity type,

said third semiconductor layer retreats on a side wall facing said fourth semiconductor layer in a central position of each of said regions from said side wall toward an opposite side or up to said opposite side, and

said connecting portion includes at least a part of said exposed surface of a portion of said second semiconductor layer which fills up a retreating portion of said third semiconductor layer.

5. The semiconductor device according to claim 4, further comprising a fifth semiconductor layer of a second conductivity type which is selectively formed in said retreating portion of said third semiconductor layer and has a higher impurity concentration than that of said second semiconductor layer.

6. The semiconductor device according to claim 1, wherein said fourth semiconductor layer is a semiconductor layer of a second conductivity type.

7. The semiconductor device according to claim 6, wherein said first main electrode is connected to exposed surfaces of said second and third semiconductor layers across an edge of said third semiconductor layer which is closer to said second main electrode.

8. The semiconductor device according to claim 6, further comprising a semiconductor well layer of a first conductivity type which is selectively formed on said first semiconductor layer and has a higher impurity concentration than that of said first semiconductor layer,

wherein said semiconductor well layer is in contact with said second semiconductor layer on a side of said second semiconductor layer which is closer to said second main electrode.

9. The semiconductor device according to claim 8, further comprising:

a substrate insulation film covering said second principal surface of said first semiconductor layer;

a semiconductor substrate covering said substrate insulation film; and

a semiconductor well layer of a first conductivity type which is selectively formed on said first semiconductor layer and has a higher impurity concentration than that of said first semiconductor layer,

wherein said semiconductor well layer is in contact with said second semiconductor layer on a side of said second semiconductor layer which is closer to said second main electrode, and has a bottom portion which reaches said substrate insulation film.

10. The semiconductor device according to claim 6, wherein said gate trench extends to a portion of said first semiconductor layer on an outside beyond said edge of said second semiconductor layer which is closer to said second main electrode, and

said gate trench projects in a direction orthogonal to an extension direction on an end closer to said second main electrode in said extension direction.

11. The semiconductor device according to claim 1, wherein said fourth semiconductor layer is a semiconductor layer of a first conductivity type having a higher impurity concentration than that of said first semiconductor layer.

12. The semiconductor device according to claim 1, further comprising:

a substrate insulation film covering said second principal surface of said first semiconductor layer; and

a semiconductor substrate covering said substrate insulation film.

13. The semiconductor device according to claim 12, wherein a bottom portion of said gate trench reaches said substrate insulation film,

said first semiconductor layer further defines an isolation trench open to said first principal surface, and

said isolation trench has an annular shape to enclose said second, third and fourth semiconductor layers and said gate trench, and has a bottom portion which reaches said substrate insulation film,

said semiconductor device further comprising:

an isolation insulation film covering an internal wall of said isolation trench; and

an isolation electrode buried in said isolation trench with said isolation insulation film interposed therebetween.

14. The semiconductor device according to claim 1, wherein a material of said first semiconductor layer is single-crystalline silicon, and

a <

100>

orientation of said single-crystalline silicon is coincident with an extension direction of said gate trench.

15. The semiconductor device according to claim 1, further comprising an insulation layer and a field plate opposite through said insulation layer in a region interposed between said first and second main electrodes in said first principal surface of said first semiconductor layer,

wherein an end of said field plate which is closer to said first main electrode is electrically connected to said first main electrode or said gate electrode, and an end of said field plate which is closer to said second main electrode is electrically connected to said second main electrode.

16. The semiconductor device according to claim 1, further comprising a bottom semiconductor layer of a first conductivity type which is selectively formed between said second principal surface of said first semiconductor layer and said second semiconductor layer and has a higher impurity concentration than that of said first semiconductor layer.