Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same

• US 6,198,168 B1
• Filed: 01/20/1998
• Issued: 03/06/2001
• Est. Priority Date: 01/20/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard, Geusic, Joseph E.
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/009,791
• Time in Patent Office: 1,141 Days
• Field of Search: 257/676, 257/735, 257/774, 257/773, 438/411
• US Class Current: 257/774
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.

Claims

1. An integrated circuit, comprising:

a semiconductor wafer having first and second surfaces;

a functional circuit formed on the first surface of the semiconductor wafer;

at least one high aspect ratio via that extends through the semiconductor wafer;

wherein the at least one high aspect ratio via comprises a high aspect ratio hole that is formed by an anodic etch and that is filled by initially filling the hole with polysilicon and then substituting aluminum for polysilicon in the hole; and

a metallization layer formed outwardly from the first surface of the semiconductor wafer that selectively couples at least one node of the functional circuit with the at least one high aspect ratio via.

2. The integrated circuit of claim 1, wherein the functional circuit includes both digital and analog integrated circuits formed on the same wafer.

3. The integrated circuit of claim 1, wherein the functional circuit includes active circuit elements.

4. The integrated circuit of claim 1, wherein the at least one high aspect ratio via comprises a low resistance connection to a ground bus.

5. The integrated circuit of claim 1, wherein the semiconductor wafer comprises a monocrystalline silicon wafer.

7. The integrated circuit of claim 1, and further comprising a pad formed on the second side of the semiconductor wafer that couples to the at least one high aspect ratio via.

6. An integrated circuit, comprising:

a semiconductor wafer having first and second surfaces;

a functional circuit formed on the first surface of the semiconductor wafer;

at least one high aspect ratio via that extends through the semiconductor wafer;

a metallization layer formed outwardly from the first surface of the semiconductor wafer that selectively couples at least one node of the functional circuit with the at least one high aspect ratio via; and

wherein the at least one high aspect ratio via comprises a via with an aspect ratio of at least 100.

13. The integrated circuit of claim 6, wherein the at least one high aspect ratio via comprises a high aspect ratio hole that is formed by an anodic etch and that is filled by substituting aluminum for polysilicon in the hole.

14. The integrated circuit of claim 6, wherein the functional circuit includes both digital and analog integrated circuits formed on the same wafer.

15. The integrated circuit of claim 6, wherein the functional circuit includes active circuit elements.

16. The integrated circuit of claim 6, wherein the at least one high aspect ratio via comprises a low resistance connection to a ground bus.

17. The integrated circuit of claim 6, wherein the semiconductor wafer comprises a monocrystalline silicon wafer.

18. The integrated circuit of claim 6, and further comprising a pad formed on the second side of the semiconductor wafer that couples to the at least one high aspect ratio via.

8. An integrated circuit, comprising:

a semiconductor wafer with a functional circuit formed in one surface thereof, and a number of high aspect ratio vias formed through the thickness of the wafer with a first end of each high aspect ratio via coupled to a metallization layer on the first surface of the wafer and a second end of the high aspect ratio via coupled to a bond pad on a second, opposite side of the semiconductor wafer;

wherein the at least one high aspect ratio via comprises a high aspect ratio hole that is formed by an anodic etch and that is filled by filling the hole with polysilicon and then substituting aluminum for polysilicon in the hole; and

a chip carrier having leads disposed on a surface of the chip carrier that are coupled to selected of the bond pads on the second surface of the semiconductor wafer when the semiconductor wafer is disposed on the chip carrier.

9. The integrated circuit of claim 8, wherein the functional circuit includes both digital and analog integrated circuits formed on the same wafer.

10. The integrated circuit of claim 8, wherein the at least one high aspect ratio via comprises a low resistance connection to a ground bus.

11. The integrated circuit of claim 8, wherein the semiconductor wafer comprises a monocrystalline silicon wafer.

12. An integrated circuit, comprising:

a semiconductor wafer with a functional circuit formed in one surface thereof, and a number of high aspect ratio vias formed through the thickness of the wafer with a first end of each high aspect ratio via coupled to a metallization layer on the first surface of the wafer and a second end of the high aspect ratio via coupled to a bond pad on a second, opposite side of the semiconductor wafer;

a chip carrier having leads disposed on a surface of the chip carrier that are coupled to selected of the bond pads on the second surface of the semiconductor wafer when the semiconductor wafer is disposed on the chip carrier; and

wherein the at least one high aspect ratio via comprises a via with an aspect ratio of at least 100.

19. The integrated circuit of claim 12, wherein the at least one high aspect ratio via comprises a high aspect ratio hole that is formed by an anodic etch and that is filled by initially filling the hole with polysilicon and then substituting aluminum for polysilicon in the hole.

20. The integrated circuit of claim 12, wherein the functional circuit includes both digital and analog integrated circuit formed on the same wafer.

21. The integrated circuit of claim 12, wherein the at least one high aspect ratio via comprises a low resistance connection to a ground bus.

22. The integrated circuit of claim 12, wherein the semiconductor wafer comprises a monocrystalline silicon wafer.

26. The integrated circuit of claim 12, wherein the at least one high aspect ratio via comprises a high aspect ratio hole that is formed by an anodic etch and that is filled by substituting aluminum for polysilicon in the hole by:

applying a layer of polysilicon to the surface of the wafer by chemical vapor deposition;

initially applying a coating of aluminum to the wafer by sputtering;

removing aluminum from the surface of the wafer by chemical mechanical polishing; and

annealing the wafer to substitute aluminum for the polysilicon in the holes.

23. An integrated circuit, comprising:

a semiconductor wafer with a functional circuit formed in one surface thereof, and a number of high aspect ratio vias formed through the thickness of the wafer with a first end of each high aspect ratio via coupled to a metallization layer on the first surface of the wafer and a second end of the high aspect ratio via coupled to a bond pad on a second, opposite side of the semiconductor wafer;

wherein the at least one high aspect ratio via comprises a high aspect ratio hole that is formed by an anodic etch and that is filled by initially filling the hole with polysilicon and then substituting aluminum for polysilicon in the hole by performing a sputtering of aluminum onto the surface of the wafer then annealing the wafer to substitute the aluminum for the polysilicon in the holes; and

a chip carrier having leads disposed on a surface of the chip carrier that are coupled to selected of the bond pads on the second surface of the semiconductor wafer when the semiconductor wafer is disposed on the chip carrier.

24. The integrated circuit of claim 23, wherein the anneal is performed at a temperature of about 500°

Celsius.

25. The integrated circuit of claim 24, wherein a thin layer of titanium on the aluminum layer to reduce the anneal temperature needed to assure substitution of aluminum for the polysilicon in the holes from about 500°

Celsius to below about 450°

Celsius.