Low dropout voltage reference

• US 6,198,266 B1
• Filed: 10/13/1999
• Issued: 03/06/2001
• Est. Priority Date: 10/13/1999
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Mercer, Mark J.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Vu, Bao Q.
• Application Number:
  US09/416,898
• Time in Patent Office: 510 Days
• Field of Search: 323/274, 323/275, 323/280, 323/281, 323/315, 323/316
• US Class Current: 323/316
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A low dropout voltage reference having three gain stages and two feedback loops, an overall loop and a secondary loop, is disclosed. The overall feedback loop establishes a desired output voltage. The secondary feedback loop provides two benefits: (1) a broadband reduction of the output impedance to ensure stability under various loading conditions and (2) an improvement in power supply rejection. The first benefit ensures that the pole created by the load capacitance and the output impedance of the amplifier doesn'"'"'t adversely affect the overall loop stability. The second benefit helps improve line regulation. The low dropout voltage reference does not rely on a capacitor connected to the output to properly compensate the overall feedback loop. Therefore, the reference will work properly for a wide range of load capacitance values.

Claims

1. A low dropout voltage reference circuit comprising:

a voltage generator core;

a first gain stage connected to the voltage generator core;

a second gain stage connected to the first gain stage;

a third gain stage connected to the second gain stage and the voltage generator core;

a current mirror connected to the first, second and third gain stages;

an overall feedback loop comprising the first gain stage, the second gain stage, and the third gain stage; and

a secondary feedback loop comprising the current mirror, the second gain stage and the third gain stage.

2. The circuit of claim 1, wherein the voltage generator core is a band-gap core circuit.

3. The circuit of claim 2, wherein the first gain stage is a differential input stage having differential inputs connected to the band-gap core circuit, and the first stage is further connected to each leg of the current mirror.

4. The circuit of claim 3, wherein the second gain stage is a differential amplifier, with a first terminal connected to a first leg of the current mirror, and a second terminal connected to a second leg of the current mirror.

5. The circuit of claim 4, wherein the second gain stage is an Output Transconductance Amplifier (OTA).

6. The circuit of claim 4, wherein the third gain stage is a p-channel output MOSFET and has a gate connected to an output of the second gain stage, a drain connected to the voltage generator core, and source connected to an input reference voltage.

7. The circuit of claim 6, wherein the current mirror connects to the drain of the output MOSFET.

8. The circuit of claim 7, wherein the current mirror comprises a pair of parasitic bipolar transistors formed in CMOS.

9. The circuit of claim 7, wherein the current mirror comprises a pair of MOSFETs.

10. The circuit of claim 8, wherein the overall feedback loop comprises an electrical loop from the drain of the output MOSFET through the differential input stage, through the differential amplifier, back to the output MOSFET.

11. The circuit of claim 10, wherein the secondary feedback loop comprises an electrical loop from the drain of the output MOSFET, through the current mirror to the differential inputs of the differential amplifier, through the differential amplifier to the gate of the output MOSFET, through the output MOSFET and back to the drain of the output MOSFET.

12. The circuit of claim 11, further comprising a first capacitance connected between the first terminal of the differential amplifier and a node, the node formed by the current mirror and the drain of the output MOSFET.

13. The circuit of claim 12, further comprising a second capacitance connected between the second terminal of the differential amplifier and a circuit ground.

14. The circuit of claim 13, wherein the first and second capacitances are equal.

15. A low dropout voltage reference circuit comprising:

a band-gap core circuit;

a differential input stage connected to the band-gap core circuit;

differential amplifier connected to the differential input stage;

an output MOSFET connected between the band-gap core circuit and an output of the differential amplifier;

a current mirror having a node, a first leg and a second leg, the mirror connected such that the node is connected to a drain of the output MOSFET, the first leg is connected to a first terminal of the differential amplifier, and the second leg is connected to a second terminal of the differential amplifier, each leg of the current mirror further connecting to the differential input stage;

an overall feedback loop comprising an electrical loop from the drain of the output MOSFET through the differential input stage, through the differential amplifier, back to the output MOSFET; and

a secondary feedback loop comprising an electrical loop from the drain of the output MOSFET, through the current mirror to the differential inputs of the differential amplifier, through the differential amplifier to the gate of the output MOSFET, through the output MOSFET and back to the drain of the output MOSFET.

16. The circuit of claim 15, wherein the differential amplifier is an Output Transconductance Amplifier (OTA).

17. The circuit of claim 16, wherein output MOSFET is a p-channel output MOSFET.

18. The circuit of claim 17, wherein the current mirror comprises a pair of parasitic bipolar transistors formed in CMOS.

19. The circuit of claim 17, wherein the current mirror comprises a pair of MOSFETs.

20. The circuit of claim 18, further comprising a first capacitance connected between the first terminal of the differential amplifier and the current mirror node.

21. The circuit of claim 20, further comprising a second capacitance connected between the second terminal of the differential amplifier and a circuit ground.

22. The circuit of claim 21, wherein the first and second capacitances are equal.

23. A low dropout voltage reference comprising:

an overall feedback loop that establishes a desired output voltage, comprising;

an electrical loop from the drain of an output MOSFET through a differential input stage, through a differential amplifier, back to the output MOSFET; and

a secondary feedback loop that provides a broadband reduction of the output impedance to ensure stability under various loading conditions, comprising;

an electrical loop from a drain of the output MOSFET, through the current mirror to differential inputs of a differential amplifier, through the differential amplifier to a gate of the output MOSFET, through the output MOSFET and back to the drain of the output MOSFET.