Configuration eprom with programmable logic

• US 6,198,303 B1
• Filed: 03/23/1999
• Issued: 03/06/2001
• Est. Priority Date: 03/25/1998
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Rangasayee, Krishna
• Primary Examiner(s): Tohar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/274,174
• Time in Patent Office: 714 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

An electronic device includes an Erasable Programmable Read-Only Memory (EPROM), a programmable logic device connected to the EPROM, and a single package enclosing the EPROM and the programmable logic device. The electronic device provides combined functionality that allows the EPROM to store configuration data for a programmable logic device, a Static Random Access Memory (SRAM), or an external programmable logic device, while the programmable logic device is configured to implement another function, such as a Joint Test Access Group interface function, an address decoder function, or a state machine function.

Claims

1. An electronic device, comprising:

a programmable logic device;

an Erasable Programmable Read-Only Memory (EPROM) connected to said programmable logic device, said EPROM storing configuration data for an external programmable logic device; and

a single package enclosing said EPROM and said programmable logic device.

2. The electronic device of claim 1 wherein said programmable logic device is configured as a Joint Test Access Group (JTAG) interface circuit.

3. The electronic device of claim 1 wherein said programmable logic device is configured as an address decoder.

4. The electronic device of claim 1 wherein said programmable logic device is configured as a state machine.

5. The electronic device of claim 1 in combination with a system bus.

6. The electronic device of claim 5 further comprising a system component connected to said system bus, said system component selected from the group consisting of:

a peripheral device, an input/output device, a microprocessor, and an external memory device.

7. A method of using a single package electronic device containing at least one Erasable Programmable Read-Only Memory (EPROM) and one programmable logic device, said method comprising the steps of:

storing data in said EPROM;

programming said programmable logic device by transferring certain of the data from said EPROM to said programmable logic device;

providing data from said EPROM to at least one external programmable logic device; and

configuring said at least one external programmable logic device according to said data from said EPROM.

8. The method of claim 7, further comprising the step of:

directing said programmable logic device to route a signal that enables said at least one external programmable logic device.

9. The method of claim 7 wherein said programming step includes the step of programming said programmable logic device as a decoder.

10. The method of claim 7 wherein said programming step includes the step of programming said programmable logic device as a JTAG interface circuit.

11. The method of claim 7 wherein said programming step includes the step of programming said programmable logic device as a state machine.

12. A self-configuring electronic system, comprising:

a single package electronic device, including;

an EPROM storing configuration data; and

a programmable logic device connected to said EPROM; and

at least one external programmable logic device interfaced to said single package electronic device, said external programmable logic device being configured in response to said configuration data from said EPROM.

13. The self-configuring electronic system of claim 12, further comprising a microprocessor electrically connected to said single package electronic device such that said microprocessor directs said programmable logic device to send said electronic signals to said at least one external programmable logic device, said electronic signals enabling said at least one external programmable logic device.

14. The self-configuring electronic system of claim 12, further comprising:

a system bus connected to said single package electronic device; and

a system element connected to said system bus, said system element selected from the group consisting of;

a peripheral device, an input/output device, a microprocessor, and an external memory device.

15. The self-configuring electronic system of claim 12 wherein said programmable logic device is configured as a decoder.

16. The self-configuring electronic system of claim 12 wherein said programmable logic device is configured as a JTAG interface circuit.

17. The self-configuring electronic system of claim 12 wherein said programmable logic device is configured as a state machine.