Flip flops

• US 6,198,324 B1
• Filed: 11/23/1999
• Issued: 03/06/2001
• Est. Priority Date: 11/25/1998
• Status: Expired due to Fees

• Current Assignee: Innurvation IP LLC
• Original Assignee: Nanopower Technologies, Inc.
• Inventors: Schober, Robert C.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/447,499
• Time in Patent Office: 469 Days
• Field of Search: 327/201, 327/202, 327/203, 327/208, 327/210, 327/211, 327/212, 327/217, 327/218
• US Class Current: 327/202
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 19/23 Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.

Claims

1. A flip-flop that is settable or resetable in response to a control input, the flip-flop comprising:

a master latch receiving an input of the flip-flop;

a logic gate coupled to receive an output of the master latch; and

a slave latch coupled to the master latch and to an output of the logic gate, wherein the master latch, the logic gate, and the slave latch are each responsive to a clock signal, wherein the master latch and the logic gate each include a plurality of transistor branches, each for coupling a corresponding node to a first power supply node or a second power supply node, and wherein the control input for setting or resetting the flip-flop is not input to any transistor branch of the master latch or the logic gate that is responsive to an active edge of the clock signal.

2. A flip-flop as recited in claim 1, wherein the control input for setting or resetting the flip-flop is not input to the slave latch.

3. A flip-flop as recited in claim 2, wherein the control input for setting or resetting the flip-flop is not applied to the input of any transistor that is in a path used to convey the state of the input of the flip-flop to an output of the flip-flop.

4. A flip-flop that is settable or resetable in response to a control input, the flip-flop comprising:

a master latch receiving an input of the flip-flop and the control input;

a logic gate coupled to receive an output of the master latch and the control input; and

a slave latch coupled to the master latch and an output of the logic gate, wherein the control input for setting or resetting the flip-flop is not input to the slave latch.

5. A flip-flop as recited in claim 4, wherein the master latch and the slave latch are each responsive to a clock signal, wherein the master latch, the slave latch, and the logic gate each include a plurality of transistor branches, each transistor branch for coupling a corresponding node to a first power supply node or a second power supply node, and wherein the control input for setting or resetting the flip-flop is not input to any transistor branch of the flip-flop that is responsive to an active edge of the clock signal.

6. A race-free flip-flop that is setable or resetable in response to a control input, the flip-flop comprising:

a master latch including

a first transistor branch coupled to receive a clock signal and a data input signal and configured to release a first output of the master latch from a first logic level in response to an active edge of the clock signal, and

a second transistor branch coupled to receive a gated clock signal and the data input signal and coupled in series with the first transistor branch and configured to release the first output of the master latch from a second logic level in response to an active edge of the gated clock signal, wherein the control input for setting or resetting the flip-flop is not input to the second transistor branch or the first transistor branch;

a logic gate coupled to receive the first output of the master latch and the clock signal and having the gated clock signal as output, the logic gate including

a third transistor branch coupled to receive the clock signal and configured to pull the gated clock signal to the second logic level in response to the active edge of the clock signal, and

a fourth transistor branch coupled in series with the third transistor branch and configured to pull the gated clock signal to the first logic level, wherein the control input for setting or resetting the flip-flop is input to the fourth transistor branch but not the third transistor branch; and

a slave latch coupled to receive the output of the logic gate, the clock signal, and a second output of the master latch, the slave latch generating an output of the flip-flop, wherein the control input for setting or resetting the flip-flop is not input to the slave latch.

7. A flip-flop as recited in claim 6, wherein the control input for setting or resetting the flip-flop is not applied to the input of any transistor that is in a path used to convey the state of the input of the flip-flop to an output of the flip-flop.