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Flip flops

  • US 6,198,324 B1
  • Filed: 11/23/1999
  • Issued: 03/06/2001
  • Est. Priority Date: 11/25/1998
  • Status: Expired due to Fees
First Claim
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1. A flip-flop that is settable or resetable in response to a control input, the flip-flop comprising:

  • a master latch receiving an input of the flip-flop;

    a logic gate coupled to receive an output of the master latch; and

    a slave latch coupled to the master latch and to an output of the logic gate, wherein the master latch, the logic gate, and the slave latch are each responsive to a clock signal, wherein the master latch and the logic gate each include a plurality of transistor branches, each for coupling a corresponding node to a first power supply node or a second power supply node, and wherein the control input for setting or resetting the flip-flop is not input to any transistor branch of the master latch or the logic gate that is responsive to an active edge of the clock signal.

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