Charge pump circuit simple in construction and free from trouble even at low voltage

• US 6,198,342 B1
• Filed: 12/08/1999
• Issued: 03/06/2001
• Est. Priority Date: 12/08/1998
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kawai, Ken
• Primary Examiner(s): Cunningham, Terry D.
• Application Number:
  US09/456,325
• Time in Patent Office: 454 Days
• Field of Search: 327/534, 327/536, 327/537, 307/110
• US Class Current: 327/536
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages

Abstract

In a charge pump circuit, the issues of increase in loss due to the backgating effect, increase in cost, risks of latch-up and charge leak and the like, which would be involved in achieving voltage reduction, are resolved with a simple circuit structure. A pump cell 31 has nMOS transistors M1-M3 and capacitors C1, C2. An auxiliary capacitor C is connected to an input node IN, and further p-well portions of the nMOS transistors M1-M3 are connected to this auxiliary capacitor C, the nMOS transistor M3 is interposed between each p-well portion and output node OUT, and the input node IN is connected to the gate of the nMOS transistor M3. Thus, with a simple circuit structure which involves only the use of the auxiliary capacitor C, voltage difference of the push-down of the p-well voltage is increased so that the deterioration of pump efficiency due to the backgating effect in the voltage reduction of power supply voltage is eliminated and that latch-up and charge leak are prevented.

Claims

1. A charge pump circuit having a plurality of pump cells connected in series, wherein a pump cell of an odd-numbered stage executes a charge pump operation for an input voltage based on a first clock signal and a second clock signal while a pump cell of an even-numbered stage executes a charge pump operation based on a third clock signal and a fourth clock signal so that an output voltage resulting from boosting the input voltage is obtained,

the pump cell being characterized in that:

drain of a first transistor and gate of a second transistor are connected to an input node;

source of the first transistor, source of the second transistor and one electrode of a first capacitor are connected to an output node;

drain of the second transistor and one electrode of a second capacitor are connected to a node connected to gate of the first transistor;

a clock input node to which one of the clock signals, whichever it is, is inputted is connected to the other electrodes of the first capacitor and the second capacitor;

one electrode of a third capacitor is connected to the input node;

a well portion of each transistor is connected to the other electrode of the third capacitor; and

that

the pump cell is equipped with switching means for electrically connecting or cutting off the well portion and the output node to or from each other.

2. The charge pump circuit according to claim 1, wherein

the pump cell further comprises:

voltage setting means for setting the input node, the output node, the node and the well portion to the same voltage when the charge pump circuit is out of operation.

3. The charge pump circuit according to claim 1, wherein

the transistors constituting the pump cell are nMOS transistors.

4. The charge pump circuit according to claim 3, wherein

the switching means operates in such a manner that:

when the voltage of the output node of the pump cell is lower than the voltage of the input node, the switching means electrically connects the well portion and the output node to each other; and

when the voltage of the output node of the pump cell is higher than the voltage of the input node, the switching means electrically cuts off the well portion and the output node from each other so that the well portion is brought into a floating state.

5. The charge pump circuit according to claim 3, wherein

a capacitance value of the third capacitor is so set that

the voltage of the well becomes lower than the voltage of source and drain of all the transistors constituting the pump cell regardless of what is operational state of the pump cell.

6. The charge pump circuit according to claim 1, wherein

the transistors constituting the pump cell are pMOS transistors.

7. The charge pump circuit according to claim 6, wherein

the switching means operates in such a manner that:

when the voltage of the output node of the pump cell is higher than the voltage of the input node, the switching means electrically connects the well portion and the output node to each other; and

when the voltage of the output node of the pump cell is lower than the voltage of the input node, the switching means electrically cuts off the well portion and the output node from each other so that the well portion is brought into a floating state.

8. The charge pump circuit according to claim 6, wherein

a capacitance value of the third capacitor is so set that

the voltage of the well becomes higher than the voltage of source and drain of all the transistors constituting the pump cell regardless of what is operational state of the pump cell.

9. The charge pump circuit according to claim 1, wherein

at least one pump cell among the pump cells connected in series is connected in parallel with another pump cell having the same structure.

10. A charge pump circuit having at least one pump cell, wherein the pump cell has a structure that:

drain of a first transistor and gate of a second transistor are connected to an input node;

source of the first transistor, source of the second transistor and one electrode of a first capacitor are connected to an output node;

drain of the second transistor and one electrode of a second capacitor are connected to a node connected to gate of the first transistor;

a clock input node to which one of clock signals, whichever it is, is inputted is connected to the other electrodes of the first capacitor and the second capacitor;

one electrode of a third capacitor is connected to the input node;

a well portion of each transistor is connected to the other electrode of the third capacitor; and

that

switching means is provided for electrically connecting or cutting off the well portion and the output node to or from each other.