Power sensing apparatus for power amplifiers
First Claim
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1. A power sensing circuit for sensing the output power of a power amplifier comprising:
- a FET device operative in a first linear mode and second saturated mode of operation, said FET having source, gate and drain electrodes; and
resistive means connected between said source electrode and a reference potential for generating a voltage drop between said source and said reference potential such that when said FET operates in said saturation mode, said voltage drop is indicative of the output power of said power amplifier.
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Abstract
In a power amplifier comprising a plurality of cascaded field effect transistors (FETs), a power sensing circuit for sensing the output power of the power amplifier comprising a FET device operative in a first linear mode and second saturated mode of operation, the FET having source, gate and drain electrodes; and a low value resistor connected between the source electrode and a reference potential for generating a voltage drop between the source and the reference potential such that when the FET operates in the saturation mode, the voltage drop is indicative of the output power of the power amplifier.
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Citations
20 Claims
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1. A power sensing circuit for sensing the output power of a power amplifier comprising:
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a FET device operative in a first linear mode and second saturated mode of operation, said FET having source, gate and drain electrodes; and
resistive means connected between said source electrode and a reference potential for generating a voltage drop between said source and said reference potential such that when said FET operates in said saturation mode, said voltage drop is indicative of the output power of said power amplifier. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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- 9. A power sensing circuit for sensing the output power of a semiconductor device which is driven via an input signal from a linear to a power saturated condition, wherein a plurality of drain finger electrodes, source finger electrodes, and gate finger electrodes are disposed on a semiconductor substrate to form said semiconductor device, and wherein said source finger electrodes are coupled to a reference potential, said power sensing circuit comprising a field effect transistor (FET) having source, gate and drain finger electrodes disposed on said semiconductor substrate, wherein said source electrode corresponding to said power sensing circuit FET is connected to said reference potential via a bond pad and a resistor, such that when said semiconductor device enters a saturated condition, said power sensing circuit FET enters saturation and a voltage drop is generated across said resistor indicative of the level of saturation of said power sensing circuit FET and which corresponds to the output power of said amplifier.
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15. A method for providing a power sensing apparatus for a power amplifier operable in a compression mode comprising the steps of:
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forming an active region at a surface of a semiconductor substrate;
forming a plurality of drain finger electrodes, source finger electrodes, and gate finger electrodes within said active region;
forming a source bus for connecting each of said source finger electrodes and coupling said source fingers to a reference potential; and
removing one of said FET source finger connections to said source bus and inserting a resistor between said one source finger electrode and said reference potential, wherein when said power amplifier enters compression the FET having said source finger coupled to said resistor also operates in compression mode, such that the voltage generated across said resistor represents a measure of the output power of said amplifier. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification