Architecture repartitioning to simplify outside-plant component of fiber-based access system

• US 6,198,558 B1
• Filed: 04/07/1998
• Issued: 03/06/2001
• Est. Priority Date: 04/07/1998
• Status: Expired due to Term

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Ellis, Donald Russell, Morris, Todd Douglas, Graves, Alan Frank
• Primary Examiner(s): NEGASH, KINFE MICHAEL
• Application Number:
  US09/056,096
• Time in Patent Office: 1,064 Days
• Field of Search: 359/125, 359/137, 359/167, 359/152, 359/119, 359/185, 370/389, 370/398, 370/452, 370/458, 370/460, 370/403, 370/521, 370/907, 348/6-7, 348/10, 348/12, 348/13, 455/5.1
• US Class Current: 398/135
• CPC Class Codes: H04L 2012/5605 Fibre
• CPC Class Codes: H04L 2012/567 Frame Relay over ATM
• CPC Class Codes: H04Q 11/0062 Network aspects
• CPC Class Codes: H04Q 11/0067 Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring
• CPC Class Codes: H04Q 11/0071 Provisions for the electrical-optical layer interface
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections
• CPC Class Codes: Y10S 370/907 Synchronous optical network, SONET

Abstract

An improved access system for use in a Fiber-In-The-Loop (FITL) communications network is disclosed. The access system comprises a host digital terminal (HDT) and a plurality of subtending optical network units (ONUs). The digital signal processing (DSP) functions traditionally executed by line interface units (LIUs) within the ONUs are migrated to the HDT, rendering the individual ONUs simpler, cheaper and more reliable. This is made possible by the provision in each ONU of an oversampling codec for sampling (and conversion) of upstream and downstream data at a very high bit rate. The large bandwidths of the data communicated between the ONUs and the HDT are easily handled by the fiber optic medium therebetween. In the HDT, DSP functions are executed by a common pool, or bank, of DSP ASICs. Decimators are provided in the HDT in order to properly format the data for processing by the DSPs. Interpolators are provided in the HDT for creating a high rate bit stream that can be easily converted to analog format by a codec. A high degree of processing efficiency can be achieved by reducing complex processing tasks to a sequence of individual steps through the DSP bank and rerouting the result of each step through the bank. Such “hair pinning” can be performed in either the upstream (subscriber-to-core-network) or downstream (core-network-to-subscriber) directions. Optionally, decimators and interpolators can be provided in the LIUs.

Claims

1. A fiber optic communication system comprising:

a host digital terminal (HDT) for connection to a core communications network; and

at least one optical network unit (ONU) for interfacing to a corresponding plurality of subscriber loops and connected by optical fiber to the HDT;

wherein, for each subscriber loop communicating with the core network, said subscriber loop transmits analog or digital data to its corresponding ONU (and vice versa) in a corresponding one of a plurality of analog formats;

said corresponding ONU transmits digital data to the HDT (and vice versa) in a common, high-bandwidth digital format; and

the HDT transmits digital data to the core network (and vice versa) in a corresponding one of a plurality of digital formats;

wherein the HDT executes digital signal processing functions for converting data from any of the plurality of digital formats to the common digital format (and vice versa).

2. The system of claim 1, wherein the at least one ONU comprises a plurality of substantially identical line interface units (LIUs) for respectively interfacing to the corresponding subscriber loops, wherein the HDT comprises a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions, and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network and destined for the LIU, and at least one second signal processing function to be executed by a second subset of the plurality of DSPs on data arriving from the LIU and destined for the core network.

3. The system of claim 2, wherein the at least one ONU further comprises an optical transceiver connected to the optical fiber and a bidirectional multiplexer connected between the optical transceiver and the plurality of LIUs, each LIU having an oversampling codec, and wherein the HDT further comprises at least one first optical transceiver connected between the optical fiber and the switch matrix and at least one second optical transceiver for connection to the core network and connected to the switch matrix.

4. A system according to claim 3, wherein the HDT further comprises a plurality of interpolators placed at the respective outputs of the first subset of DSPs for increasing the rate of data destined for the LIUs of the at least one ONU, and a plurality of decimators placed at the respective inputs of the second set of DSPs for reducing the rate of data arriving from the LIUs of the at least one ONU.

5. A system according to claim 3, wherein at least one LIU further comprises a decimator and an interpolator placed between the codec and the multiplexer, wherein the decimator decreases the rate of data flowing to the multiplexer and the interpolator increases the rate of data flowing to the codec.

6. A system according to claim 3, wherein the HDT further comprises a plurality of random access memories (RAMs) that store programs run by respective DSPs.

7. A system according to claim 6, wherein the HDT further comprises a control processor for controlling the switch matrix, thereby to selectively interconnect the at least one first and second transceiver to the plurality of DSPs.

8. A system according to claim 7, wherein the control processor is connected to the RAMs and can change the respective programs, thereby to change the signal processing functions executed by the associated DSPs.

9. A system according to claim 3, wherein the HDT further comprises a loop status processor for monitoring voltage and current conditions on each of the plurality of subscriber loops.

10. A system according to claim 3, wherein the HDT further comprises an OAM processor for controlling the operation of the multiplexer in the at least one ONU.

11. A system according to claim 3, wherein the switch matrix comprises a first digital switch connected between the at least one first transceiver and the DSPs, and a second digital switch connected between the DSPs and the at least one second transceiver.

12. A system according to claim 11, wherein the first and second digital switches are connected by a bidirectional hair pin connection, whereby data output by the first digital switch may be routed to the second digital switch and data output by the second digital switch may be routed to the first digital switch, thereby to traverse the DSPs a plurality of times in sequence.

13. A system according to claim 3, wherein the at least one ONU further comprises an ONU control processor connected between the transceiver and the multiplexer for interpreting control instructions received from the HDT and for sending status information to the HDT.

14. A system according to claim 13, wherein each LIU further comprises a ringing generator, a loop status detector and an analog front end for generating and interpreting currents and voltages on the associated subscriber loop.

15. A system according to claim 14, wherein the ringing generator and loop status detector on each LIU are connected to the multiplexer of the corresponding ONU.

16. A system according to claim 14, wherein the ringing generator and loop status detector on each LIU are connected to the ONU control processor of the corresponding ONU.

17. A system according to claim 14, wherein the analog front end on each LIU interfaces to a copper twisted pair subscriber loop.

18. A system according to claim 14, wherein the analog front end on each LIU interfaces to a coaxial cable subscriber loop.

19. A system according to claim 3, wherein the HDT and at least one ONU are interconnected in a passive optical network configuration.

20. A system according to claim 3, wherein the HDT and at least one ONU are interconnected in a SONET ring configuration.

21. A system according to claim 3, wherein the HDT and at least one ONU are interconnected by point-to-point link.

22. A system according to claim 3, wherein one of the signal processing functions consists of converting mu-law encoded pulse code modulation (PCM) data samples arriving from the core network into linearly encoded data samples destined for at least one LIU in the at least one ONU.

23. A system according to claim 3, wherein one of the signal processing functions consists of converting linearly encoded data samples arriving from at least one LIU in the at least one ONU into mu-law encoded pulse code modulation (PCM) data samples destined for the core network.

24. A system according to claim 22, wherein another of the signal processing functions consists of converting linearly encoded data samples arriving from at least one LIU in the at least one ONU into mu-law encoded PCM data samples destined for the core network.

25. A system according to claim 3, wherein one of the signal processing functions consists of reassembling a Frame Relay data packet from segments of the Frame Relay data packet contained in the payload of respective ATM cells.

26. A system according to claim 3, wherein one of the signal processing functions consists of constructing a line coded DS-1 data stream from a Frame Relay data packet.

27. A system according to claim 3, wherein one of the signal processing functions consists of regenerating a DS-1 digital signal from an oversampled distorted line coded DS-1 signal.

28. A system according to claim 3, wherein one of the signal processing functions consists of extracting a Frame Relay packet from a the payload of a DS-1 data digital signal.

29. A system according to claim 3, wherein one of the signal processing functions consists of segmenting a Frame Relay data packet and inserting the segments into the payload of respective ATM cells.

30. In a fiber optic communication system comprising a host digital terminal (HDT) for connection to a core communications network and at least one optical network unit (ONU) for interfacing to a corresponding plurality of subscriber loops and connected by optical fiber to the HDT;

wherein the HDT comprises a digital switch matrix and a plurality of programmable digital signal processors (DSPs) executing respective processing functions and connected to the digital switch matrix, a method of communicating data between the HDT and the at least one ONU, comprising;

in a downstream direction, the switch matrix routing data received by the HDT from the core network in any of a plurality of distinct digital formats to selected ones of the DSPs;

the DSPs performing respective processing functions, yielding downstream data in a common, high-bandwidth digital format;

the switch matrix routing the downstream data to the at least one ONU; and

in an upstream direction, the switch matrix routing data received from the at least one ONU in said common, high-bandwidth digital format to selected ones of the DSPs;

the DSPs performing respective processing functions, yielding upstream data in at least one of said plurality of distinct digital formats;

the switch matrix routing the upstream data to the core network.

31. A method according to claim 30, further comprising in the downstream direction, the switch matrix routing the downstream data back to the DSPs at least once prior to routing it to the at least one ONU;

and in the upstream direction, the switch matrix routing the upstream data back to the DSPs at least once prior to routing it to the core network.

32. A method according to claim 30, further comprising in the downstream direction, the downstream data being interpolated prior to being routed to the at least one ONU;

and in the upstream direction, the data received from the at least one ONU being decimated prior to being processed by the DSPs.

33. A method according to claim 30, wherein the data being sent to the at least one ONU is organized into frames, wherein each frame comprises a number of downstream subframes, wherein each downstream subframe within a frame is destined for a particular ONU and comprises a traffic field sectioned into groups of time slots, wherein each group of time slots is destined for a separate line interface unit (LIU) in said ONU, wherein each LIU provides data in a specific format to a respective subscriber, the number of time slots in a group being dependent on the specific data format provided by the associated LIU.

34. A met hod according to claim 33, wherein the data being sent by the at least one ONU is organized into upstream subframes comprising a traffic field sectioned into groups of time slots, wherein each group of time slots originates from a separate LIU in the ONU, the number of slots in a group being dependent on the specific data format provided by the associated LIU.

35. A method according to claim 33, wherein each downstream subframe further comprises a control field containing instructions for configuring a multiplexer on the ONU for which said downstream subframe is destined.

36. A method according to claim 34, wherein each downstream subframe further comprises a control field containing instructions for timing the transmission of upstream subframes by the ONU for which said downstream subframe is destined.

37. A method according to claim 33, wherein each downstream subframe further comprises an address field for identifying the ONU for which said downstream subframe is destined.

38. A method according to claim 34, wherein each upstream subframe further comprises an address field for identifying the ONU from which said upstream subframe originates.

39. A method according to claim 34, wherein pairs of upstream subframes transmitted by the at least one ONU are separated by a guard band of variable length.

40. A method according to claim 30, wherein the data received from and transmitted to the core network by the HDT is formatted by a signalling processor in the HDT.

41. A host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising:

a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions;

at least on first optical transceiver connected between the optical fiber and the switch matrix;

at least one second optical transceiver for connection to the core network and connected to the switch matrix; and

means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU, and at least one second signal processing function to be executed by a second subset of the plurality of DSPs on data arriving from the LIU through the at least one first optical transceiver and destined for the core network.

42. An HDT according to claim 41, further comprising a plurality of interpolators placed at the respective outputs of the first subset of DSPs for increasing the rate of data destined for the LIUs of the at least one ONU, and a plurality of decimators placed at the respective inputs of the second set of DSPs for reducing the rate of data arriving from the LIUs of the at least one ONU.

43. An HDT according to claim 41, further comprising a plurality of random access memories (RAMs) that store programs run by respective DSPs.

44. An HDT according to claim 43, further comprising a control processor for controlling the switch matrix, thereby to selectively interconnect the at least one first and second transceiver to the plurality of DSPs.

45. An HDT according to claim 44, wherein the control processor is connected to the RAMs and can change the respective programs, thereby to change the signal processing functions executed by the associated DSPs.

46. An HDT according to claim 41, further comprising a loop status processor for monitoring voltage and current conditions on the subscriber loops.

47. An HDT according to claim 41, further comprising an OAM processor for controlling the operation of the at least one ONU.

48. An HDT according to claim 41, wherein the switch matrix comprises a first digital switch connected between the at least one first transceiver and the DSPs, and a second digital switch connected between the DSPs and the at least one second transceiver.

49. An HDT according to claim 48, wherein the first and second digital switches are connected by a bidirectional hair pin connection, whereby data output by the first digital switch is routed to the second digital switch and data output by the second digital switch is routed to the first digital switch.

50. An HDT according to claim 41, wherein one of the signal processing functions consists of converting mu-law encoded pulse code modulation (PCM) data samples arriving from the core network into linearly encoded data samples destined for at least one LIU in the at least one ONU.

51. An HDT according to claim 41, wherein one of the signal processing functions consists of converting linearly encoded data samples arriving from at least one LIU in the at least one ONU into mu-law encoded pulse code modulation (PCM) data samples destined for the core network.

52. An HDT according to claim 50, wherein another of the signal processing functions consists of converting linearly encoded data samples arriving from at least one LIU in the at least one ONU into mu-law encoded PCM data samples destined for the core network.

53. An HDT according to claim 41, wherein one of the signal processing functions consists of reassembling a Frame Relay data packet from segments of the Frame Relay data packet contained in the payload of respective ATM cells.

54. An HDT according to claim 41, wherein one of the signal processing functions consists of constructing a line coded DS-1 data stream from a Frame Relay data packet.

55. An HDT according to claim 41, wherein one of the signal processing functions consists of regenerating a DS-1 digital signal from an oversampled distorted line coded DS-1 signal.

56. An HDT according to claim 41, wherein one of the signal processing functions consists of extracting a Frame Relay packet from a the payload of a DS-1 data digital signal.

57. An HDT according to claim 41, wherein one of the signal processing functions consists of segmenting a Frame Relay data packet and inserting the segments into the payload of respective ATM cells.