Ferroelectric memory devices which utilize boosted plate line voltages to improve reading reliability and methods of operating same

• US 6,198,651 B1
• Filed: 09/08/1998
• Issued: 03/06/2001
• Est. Priority Date: 09/08/1997
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ki-Nam, Lee, Jin-Woo, Jung, Dong-Jin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US09/149,366
• Time in Patent Office: 910 Days
• Field of Search: 365/145, 365/149
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

Ferroelectric memory devices include a plate line, a bit line, a ferroelectric memory cell containing a first access transistor and a first ferroelectric capacitor electrically connected in series between the bit line and the plate line, and a word line electrically connected to a gate electrode of the first access transistor. A row decoder and a preferred plate line pulse generator are also provided to generate a write voltage of first magnitude (e.g., Vcc) on the plate line during a write time interval and a read voltage of a second magnitude (e.g., Vcc+α), greater than the first magnitude, on the plate line during a read time interval. These different magnitudes of the write and read voltage for the plate line are generated in response to a control signal (CP), so that during a read operation, the magnitude of the change in voltage across the ferroelectric capacitor will be sufficient to enable a complete charge transfer of 2Q_R when the ferroelectric memory cell is storing a data 1 value. The plate line pulse generator may comprise a pulse generator, a voltage boosting circuit having an input electrically coupled to an output of the pulse generator and a switch circuit to electrically couple an output of the pulse generator to an output of the plate line pulse generator when the control signal is in a first logic state (during a write operation) and electrically couple an output of the voltage boosting circuit to the output of the plate line pulse generator when the control signal is in a second logic state (during a read operation).

Claims

1. An integrated circuit memory device, comprising:

a plate line;

a bit line;

a ferroelectric memory cell comprising a first access transistor and a first ferroelectric capacitor electrically connected in series between said bit line and said plate line;

a word line electrically connected to a gate electrode of the first access transistor; and

means, electrically coupled to said plate line and responsive to a control signal, for generating a write voltage having a maximum first magnitude on said plate line during a write time interval and a read voltage having a maximum second magnitude, greater than the maximum first magnitude, on said plate line during a read time interval.

2. An integrated circuit memory device, comprising:

a plate line;

a bit line;

a ferroelectric memory cell comprising a first access transistor and a first ferroelectric capacitor electrically connected in series between said bit line and said plate line;

a word line electrically connected to a gate electrode of the first access transistor; and

means, electrically coupled to said plate line and responsive to a control signal, for generating a write voltage having a first magnitude on said plate line during a write time interval and a read voltage having a second magnitude, greater than the first magnitude, on said plate line during a read time interval;

wherein said generating means comprises a plate line pulse generator, said plate line pulse generator comprising;

a pulse generator;

a voltage boosting circuit having an input electrically coupled to an output of said pulse generator; and

a switch circuit to electrically couple an output of said pulse generator to an output of said plate line pulse generator when the control signal is in a first logic state and electrically couple an output of said voltage boosting circuit to the output of said plate line pulse generator when the control signal is in a second logic state, opposite the first logic state.

3. The memory device of claim 2, further comprising:

a reference plate line;

a reference bit line;

a ferroelectric reference cell containing a second access transistor and a second ferroelectric capacitor electrically connected in series between said reference bit line and said reference plate line;

a reference word line electrically connected to a gate electrode of the second access transistor; and

wherein said generating means comprises means for generating the write voltage of first magnitude on said reference plate line during the write time interval and the read voltage of second magnitude on said reference plate line during the read time interval.

4. The memory device of claim 3, further comprising a row decoder having outputs electrically coupled to said plate line and said reference plate line and an input electrically coupled to the output of said plate line pulse generator.

5. The memory device of claim 4, wherein said switch circuit comprises:

a PMOS transistor electrically connected in series between the output of said plate line pulse generator and the output of said pulse generator; and

an NMOS transistor electrically connected in series between the output of said plate line pulse generator and the output of said voltage boosting circuit.

6. The memory device of claim 5, further comprising a sense amplifier having first and second inputs electrically coupled to said bit line and said reference bit line, respectively.

7. An integrated circuit memory device, comprising:

a plurality of plate lines;

a plurality of bit lines;

an array of ferroelectric memory cells, each of the memory cells in said array thereof comprising an access transistor and a ferroelectric capacitor electrically connected in series between a corresponding bit line and a corresponding plate line;

a plurality of word lines electrically connected to gate electrodes of the access transistors in said array of ferroelectric memory cells;

a plate line pulse generator which generates a write plate line voltage of first magnitude at an output thereof during a write time interval and generates a read plate line voltage of a second magnitude, greater than the first magnitude, at the output during a read time interval; and

a row decoder to drive said plurality of plate lines and said plurality of word lines and electrically couple the output of said plate line pulse generator to a plate line in the plurality thereof during the read and write time intervals.

8. The memory device of claim 7, wherein said generating means comprises a plate line pulse generator, comprises:

a pulse generator;

a voltage boosting circuit having an input electrically coupled to an output of said pulse generator; and

a switch circuit to electrically couple an output of said pulse generator to an output of said plate line pulse generator when the control signal is in a first logic state and electrically couple an output of said voltage boosting circuit to the output of said plate line pulse generator when the control signal is in a second logic state, opposite the first logic state.

9. The memory device of claim 8, wherein said switch circuit comprises:

a PMOS transistor electrically connected in series between the output of said plate line pulse generator and the output of said pulse generator; and

an NMOS transistor electrically connected in series between the output of said plate line pulse generator and the output of said voltage boosting circuit.

10. A method of operating a ferroelectric memory device, comprising the steps of:

driving a plate line of a ferroelectric memory cell with a plate line voltage having a maximum first magnitude, during a write time interval;

driving the plate line of the ferroelectric memory cell with a plate line voltage having a maximum second magnitude, greater than the maximum first magnitude, during a read time interval; and

sensing a potential of a bit line electrically coupled to the ferroelectric memory cell during the read time interval.

11. A method of operating a ferroelectric memory device, comprising the steps of:

driving a plate line of a ferroelectric memory cell with a plate line voltage of a first magnitude, during a write time interval;

driving the plate line of the ferroelectric memory cell with a plate line voltage of a second magnitude, greater than the first magnitude, during a read time interval;

sensing a potential of a bit line electrically coupled to the ferroelectric memory cell during the read time interval;

driving a reference plate line of a ferroelectric reference cell with a reference plate line voltage of the first magnitude, during the write time interval;

driving the reference plate line of the ferroelectric memory cell with a reference plate line voltage of the second magnitude, during the read time interval;

sensing a potential of a reference bit line electrically coupled to the ferroelectric reference cell during the read time interval; and

amplifying a difference in potential between the sensed potential of the bit line and the sensed potential of the reference bit line.