Non-volatile semiconductor integrated memory device
First Claim
1. A semiconductor integrated memory device comprising a plurality of memory cells, which are arranged in the form of a matrix and each of which comprises:
- a memory capacitor having at least a first electrode, a second electrode facing said first electrode, and a ferroelectric thin-film sandwiched between said first and second electrodes;
a reference capacitor having at least a third electrode connected to said first electrode, a fourth electrode facing said third electrode, and a dielectric thin-film sandwiched between said third and fourth electrodes;
a read transistor having a gate electrode connected to said first and third electrodes; and
a control transistor for adjusting potentials of storage node which is a connection point of said first electrode of said memory capacitor, said third electrode of said reference capacitor and said gate electrode of said read transistor.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor integrated memory device comprises a plurality of memory cell blocks, which are formed in the form of a matrix and each of which comprises: a memory cell chain including a plurality of units, each comprising a ferroelectric memory capacitor and a control transistor connected in parallel thereto; a reference capacitor of a unit comprising a reference capacitor and a control transistor connected in parallel thereto; a read transistor having a gate electrode connected to a connection point between the memory cell chain and the reference cell; and a control transistor for adjusting potentials of storage node which is a connection point of the first electrode of the memory capacitor, the third electrode of the reference capacitor and the read transistor. With this construction, the semiconductor integrated memory device is able to be easily produced, to stably retain a ferroelectric polarization and to scale down.
173 Citations
17 Claims
-
1. A semiconductor integrated memory device comprising a plurality of memory cells, which are arranged in the form of a matrix and each of which comprises:
-
a memory capacitor having at least a first electrode, a second electrode facing said first electrode, and a ferroelectric thin-film sandwiched between said first and second electrodes;
a reference capacitor having at least a third electrode connected to said first electrode, a fourth electrode facing said third electrode, and a dielectric thin-film sandwiched between said third and fourth electrodes;
a read transistor having a gate electrode connected to said first and third electrodes; and
a control transistor for adjusting potentials of storage node which is a connection point of said first electrode of said memory capacitor, said third electrode of said reference capacitor and said gate electrode of said read transistor. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A semiconductor integrated memory device comprising a plurality of memory cell blocks, which are arranged in the form of a matrix and each of which comprises:
-
a memory cell column having a plurality of memory cells connected in series, each memory cell comprising a memory capacitor, which has at least a first electrode, a second electrode facing said first electrode, and a ferroelectric thin-film sandwiched between said first and second electrodes, and a control transistor connected to between said first and second electrodes;
a reference capacitor having at least a third electrode, which electrically connected to said first electrode of said memory capacitor arranged at one end of said memory cell column, a fourth electrode facing said third electrode, and a dielectric thin-film sandwiched between said third and fourth electrodes; and
a read transistor having a gate electrode electrically connected to said first and third electrodes. - View Dependent Claims (7, 8, 9, 10)
-
-
11. A semiconductor integrated memory device comprising a plurality of memory cell blocks, which are arranged in the form of a matrix and each of which comprises:
-
a NAND type memory cell column comprising a plurality of selecting MOS transistors connected in series, and a plurality of memory capacitors of dielectric films, each of which is sandwiched between a storage electrode connected to a common main electrode of each of said selecting MOS transistors, and a plate electrode facing said storage electrode;
a reference capacitor electrically connected to a main electrode of said selecting transistor arranged at one end of said memory cell column; and
a read transistor having a gate electrode electrically connected to a connection part between a main electrode of said selecting MOS transistor and a main electrode of said reference capacitor. - View Dependent Claims (12, 13, 14, 15, 16, 17)
-
Specification