Asymmetric memory cell for single-ended sensing

• US 6,198,656 B1
• Filed: 12/23/1999
• Issued: 03/06/2001
• Est. Priority Date: 12/23/1999
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhang, Kevin X.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Tran, M.
• Application Number:
  US09/470,688
• Time in Patent Office: 439 Days
• Field of Search: 365/230.06, 365/154
• US Class Current: 365/154
• CPC Class Codes: G11C 11/412 using field-effect transistors only

Abstract

In one embodiment, an apparatus including an asymmetrical memory cell having a first inverter and a second inverter is provided. The first inverter is larger than said second inverter.

Claims

1. An apparatus comprising:

an asymmetrical memory cell having

a first inverter and a second inverter, said first inverter is larger than said second inverter;

a first pass gate transistor connected to an output of the first inverter; and

a second pass gate transistor connected to an output of the second inverter;

wherein the first pass gate transistor is larger than the second pass gate transistor.

2. The apparatus of claim 1 wherein the first inverter further comprises a first pull-down transistor, and the second inverter further comprises a second pull-down transistor, wherein the first pull-down transistor is larger than the second pull-down transistor.

3. The apparatus of claim 2, further comprising a sensing circuit connected to an output of the first pass gate transistor to read data stored in the asymmetrical memory cell.

4. An apparatus comprising:

an asymmetrical memory cell having a first inverter and a second inverter, said first inverter is larger than said second inverter;

a bit line connected to an output of the asymmetrical memory cell;

a sensing circuit having an input connected to the bit line and an output to output a signal representing the data stored in the asymmetrical memory cell;

a first pass gate transistor connected to an output of the first inverter; and

a second pass gate transistor connected to an output of the second inverter;

wherein the first pass gate transistor is larger than the second pass gate transistor.

5. The apparatus of claim 4 wherein the first inverter further comprises a first pull-down transistor, and the second inverter further comprises a second pull-down transistor, wherein the first pull-down transistor is larger than the second pull-down transistor.

6. The apparatus of claim 4, wherein the sensing circuit comprises an inverter.

7. An apparatus comprising:

an asymmetrical memory means for storing data, said asymmetrical memory means having a first inverter means for storing a bit and a second inverter means for storing a complementary bit, said first inverter means is larger than said second inverter means;

sensing means for sensing the data stored in the asymmetrical memory cell, said sensing means having an input connected an output of the asymmetrical memory cell and an output to output a signal representing the data stored in the asymmetrical memory cells;

a first pass gate transistor connected to an output of the first inverter means; and

a second pass gate transistor connected to an output of the second inverter means;

wherein the first pass gate transistor is larger than the second pass gate transistor.

8. The apparatus of claim wherein the first inverter means further comprises a first pull-down transistor, and the second inverter means further comprises a second pull-down transistor, wherein the first pull-down transistor is larger than the second pull-down transistor.

9. The apparatus of claim 8, wherein the sensing means comprises a sensing circuit connected to an output of the first pass gate transistor to read data stored in the asymmetrical memory cell.

10. The apparatus of claim 9 wherein the sensing circuit comprises an inverter.