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Asymmetric memory cell for single-ended sensing

  • US 6,198,656 B1
  • Filed: 12/23/1999
  • Issued: 03/06/2001
  • Est. Priority Date: 12/23/1999
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • an asymmetrical memory cell having a first inverter and a second inverter, said first inverter is larger than said second inverter;

    a first pass gate transistor connected to an output of the first inverter; and

    a second pass gate transistor connected to an output of the second inverter;

    wherein the first pass gate transistor is larger than the second pass gate transistor.

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