High density flash memory architecture with columnar substrate coding

• US 6,198,658 B1
• Filed: 10/08/1999
• Issued: 03/06/2001
• Est. Priority Date: 10/08/1999
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics America Incorporated (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics America Incorporated (SK Hynix Inc.)
• Inventors: Klinger, Pavel, Yoon, Sukyoon, Yoon, Joo Young
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US09/415,770
• Time in Patent Office: 515 Days
• Field of Search: 365/185.18, 365/185.05, 365/185.06, 257/314, 257/315, 257/316, 257/371, 257/390
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/565 Multilevel memory comprising elements in triple well structure
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Instead of using a common substrate (101) for each sector of a flash memory, trenches are used to isolate columnar active substrate regions (304) of the substrate (101), and independent access to each of these columnar regions (304) is provided. First, the independent access to each of these columnar regions (304) provides a capability for achieving more precise control over the voltage on the floating gates (106). For example, flash memory in accordance with the present invention is better suited for multi-level storage (storing of more than 1 bit of information per cell). Second, the independent access to each of these columnar regions (304) also provides a capability for areas of flash memory smaller than an entire sector to be erased at one time. Finally, since both programming and erasing is achieved by way of cold electron tunneling from the columnar active substrate region (304), no high voltages need to be applied to either the drain (102) or source (104). This is advantageous in that the minimum distance required by cell punchthrough is reduced. Hence, higher densities of flash memory may be achieved.

Claims

1. A flash memory comprising:

a semiconductor substrate;

a plurality of trenches separating the semiconductor substrate into a plurality of columnar active substrate regions;

a plurality of flash memory cells formed in each of the columnar active substrate regions; and

circuitry for providing independent electronic access to each of the columnar active substrate regions,

where the semiconductor substrate includes a multiple well structure, and the trenches extend for an entire depth of a top well of the triple well structure.

2. The flash memory of claim 1, where the trenches comprise deep trenches filled with oxide.

3. The flash memory of claim 1, where the trenches comprise deep ion implants below shallow trenches filled with oxide.

4. The flash memory of claim 1, where the circuitry for providing independent electronic access includes contacts at ends of the columnar active substrate regions.

5. The flash memory of claim 1, where the circuitry for providing independent electronic access includes in-array contacts to the columnar active substrate regions.

6. The flash memory of claim 1, where connections to sources of the flash memory cells are formed using local interconnect.

7. The flash memory of claim 1, where individual access to bitlines during erase is provided by way of the columnar active substrate regions.

8. The flash memory of claim 7, where during programming an algorithm uses the individual access to bitlines to correct for overshoot.

9. The flash memory of claim 8, where more than one bit of data is stored per memory cell.

10. The flash memory of claim 1, where an area smaller than an entire sector is erased at one time.

11. The flash memory of claim 10, where the area comprises one wordline.

12. The flash memory of claim 10, where common source lines are used, and the area comprises two wordlines.

13. The flash memory of claim 10, where the area comprises a single cell.

14. The flash memory of claim 1, where during operation of the flash memory only low magnitude voltages are applied to drains and sources of the flash memory cells.

15. The flash memory of claim 14, where during operation a maximum magnitude voltage of less than one volt is applied to the drains and sources of the flash memory cells, and the maximum magnitude voltage is applied during a read operation.

16. The flash memory of claim 14, where a minimum distance required by cell punchthrough is thereby reduced, and so higher density of the flash memory cells is achieved.

17. The flash memory of claim 1, further comprising:

floating gates of the flash memory cells;

a set of wordlines including control gates of the flash memory cells;

drain contacts through oxide to drains of the flash memory cells;

a set of drain lines connecting to the drain contacts;

a set of source lines connecting to sources of the flash memory cell;

substrate contacts through oxide to the columnar active substrate regions; and

a set of substrate lines connecting to the substrate contacts, the set of substrate lines providing for the independent electronic access to each of the columnar active substrate regions.

18. The flash memory of claim 17, where the set of source lines comprise a local interconnect layer.

19. The flash memory of claim 18, where the local interconnect layer comprises tungsten.

20. The flash memory of claim 17, where

the set of source lines comprise a local interconnect layer;

the set of drain lines comprise a first metal layer;

the floating gates comprise a first polysilicon layer;

the set of wordlines comprise a second polysilicon layer; and

the set of substrate lines comprise a third polysilicon layer.

21. The flash memory of claim 17, where the set of drain lines comprise a first set of bitlines, and the set of substrate lines comprise a second set of bitlines.

22. The flash memory of claim 21, where the first set of bitlines is used to provide access to the flash memory cells during read operations, and the second set of bitlines is used to provide access to the flash memory cells during program and erase operations.