Hierarchical dynamic memory array architecture using read amplifiers separate from bit line sense amplifiers

• US 6,198,682 B1
• Filed: 06/10/1999
• Issued: 03/06/2001
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/329,975
• Time in Patent Office: 635 Days
• Field of Search: 365/207, 365/190, 365/208, 365/205, 365/189.01
• US Class Current: 365/207
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation sense amplifier timing G11C7/06, G11C7/08
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A high performance dynamic memory array architecture includes a row of bit line sense amplifiers between array blocks. Each bit line sense amplifier is shared between two pairs of bit lines. Half of the bit line pairs within each array block are served by a sense amplifier located above the array block, and the remaining half are served by a sense amplifier located below the array block. A read amplifier in the read path, which is separate from the bit line sense amplifier, is used to develop signal on a bus line before bit line sensing has occurred. This read amplifier may be connected to the bit lines, the internal sense amplifier nodes, a local I/O line, or a local output line. In a preferred embodiment, a second stage amplifier further buffers the signal and drives a pair of global output lines which extend the full height of the memory bank to respective I/O circuits.

Claims

1. In an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, a method of operating the integrated circuit comprising:

developing on a first bus a first read signal for a selected memory cell prior to latching a bit line sense amplifier coupled to the selected memory cell, said first read signal corresponding to a voltage level previously stored within the selected memory cell;

wherein the first bus is a bidirectional bus.

2. A method as in claim 1 wherein the first read signal on the first bus begins to develop substantially when a selected word line is driven active.

3. A method as in claim 1 further comprising:

developing on a second bus a second read signal corresponding to the first read signal prior to latching the bit line sense amplifier coupled to the selected memory cell, said second read signal thereby also corresponding to the voltage level previously stored within the selected memory cell.

4. A method as in claim 1 wherein the first bus comprises a complementary pair of local input/output lines.

5. A method as in claim 1 wherein the first bus comprises a complementary pair of global input/output lines.

6. An integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, said integrated circuit comprising:

a first array block including a first plurality of true and complement bit line pairs;

a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, for sensing a differential signal on the respective bit line pair corresponding to a voltage level previously stored within a respective memory cell of the respective bit line pair which respective memory cell is enabled by a selected word line, and for restoring a voltage level corresponding to the previously stored voltage level into the respective memory cell;

a first complementary pair of local bus lines associated with and traversing perpendicular to each of the first plurality of bit line pairs;

a first plurality of read amplifiers, each coupled to receive on a respective pair of complementary input nodes thereof a differential signal associated with a respective one of the first plurality of bit line pairs and, when selected, to drive a corresponding differential signal onto the first complementary pair of local bus lines;

a first complementary pair of global bus lines associated with, and traversing parallel to, the first plurality of bit line pairs and further associated with a respective plurality of bit line pairs located within respective array blocks other than the first array block; and

a first bus line amplifier located in close physical proximity to the first plurality of bit line sense amplifiers and arranged to receive on a first pair of complementary input nodes thereof the corresponding differential signal on the first complementary pair of local bus lines and, when selected, to drive a corresponding differential signal onto the first complementary pair of global bus lines.

7. An integrated circuit as in claim 6 further comprising a processor.

8. An integrated circuit as in claim 6 wherein capacitive loading presented by each respective read amplifier'"'"'s complementary input nodes is small relative to a total capacitance of the corresponding bit line pair.

9. An integrated circuit as in claim 6 wherein each read amplifier, when unselected, presents a capacitive load at its complementary input nodes which is less than the full channel capacitance of transistors within the read amplifier to which the complementary input nodes are connected.

10. An integrated circuit as in claim 6 further comprising:

a second plurality of true and complement bit line pairs within the first array block located substantially adjacent to the first plurality of true and complement bit line pairs;

a second plurality of bit line sense amplifiers, each coupled to a respective one of the second plurality of bit line pairs, for sensing a differential signal on the respective bit line pair corresponding to a voltage level previously stored within a respective memory cell of the respective bit line pair which respective memory cell is enabled by the selected word line, and for restoring a voltage level corresponding to the previously stored voltage level into the respective memory cell;

a second complementary pair of local bus lines associated with and traversing perpendicular to each of the second plurality of bit line pairs; and

a second plurality of read amplifiers, each coupled to receive on a respective pair of complementary input nodes thereof a differential signal associated with a respective one of the second plurality of bit line pairs and, when selected, to drive a corresponding differential signal onto the second complementary pair of local bus lines;

wherein the first complementary pair of global bus lines is also associated with the second plurality of bit line pairs; and

wherein the first bus line amplifier is also located in close physical proximity to the second plurality of bit line sense amplifiers and is arranged to receive on a second pair of complementary input nodes thereof the corresponding differential signal on the second complementary pair of local bus lines and, when selected, to drive a corresponding differential signal onto the first complementary pair of global bus lines.

11. An integrated circuit as in claim 10 wherein the first bus line amplifier includes provision to select between its first pair of complementary input nodes and its second pair of complementary input nodes.

12. An integrated circuit as in claim 10 wherein:

the first bus line amplifier is generally located between the first plurality of read amplifiers and the second plurality of read amplifiers.

13. An integrated circuit as in claim 10 wherein:

the first bus line amplifier is generally located in line with a group of word line straps for certain word lines within the first array block.

14. An integrated circuit as in claim 10 wherein each of the read amplifiers is selected by switching the gate terminal of a single transistor per bit line pair.

15. An integrated circuit as in claim 14 wherein:

each of the first plurality of read amplifiers is selected by also switching the gate terminal of a second transistor associated with the first plurality of true and complement bit line pairs, said second transistor arranged in series with a parallel combination of the respective single transistors for each true and complement bit line of the first plurality of complementary bit line pairs; and

each of the second plurality of read amplifiers is selected by also switching the gate terminal of a second transistor associated with the second plurality of true and complement bit line pairs, said second transistor arranged in series with a parallel combination of the respective single transistors for each true and complement bit line of the second plurality of complementary bit line pairs.

16. An integrated circuit as in claim 10 wherein each of the first and second plurality of bit line sense amplifiers includes:

a true internal sense amplifier node and a complement internal sense amplifier node, together forming a complementary pair of internal sense amplifier nodes; and

a first pair of transistors respectively coupling the true and complement internal sense amplifier nodes to the true and complement bit lines of the respective one of the first and second plurality of bit line pairs.

17. An integrated circuit as in claim 16 wherein each of the first and second plurality of bit line sense amplifiers includes a second pair of transistors respectively coupling its true and complement internal sense amplifier nodes to a corresponding second pair of true and complement bit lines located within an array block adjacent to the first array block.

18. An integrated circuit as in claim 16 wherein:

the pair of complementary input nodes of each respective one of the first and second plurality of read amplifiers are respectively coupled directly to the complementary pair of internal sense amplifier nodes of the respective one of the first and second plurality of bit line sense amplifiers.

19. An integrated circuit as in claim 18 wherein:

each of the first and second pluralities of read amplifiers includes a respective enable input; and

each respective enable input is coupled to a respective select signal which is responsive to a respective column select signal and which select signal occurs, for a selected read amplifier, at approximately a time when a selected word line within the first array block is driven active and substantially before the plurality of bit line sense amplifiers begin to latch.

20. An integrated circuit as in claim 18 wherein:

each respective read amplifier comprises a differential transistor pair having a common source node; and

the complementary input nodes of each respective read amplifier comprise respective gate terminals of the differential transistor pair.

21. An integrated circuit as in claim 20 wherein the differential transistor pair of each respective read amplifier comprises an N-channel transistor pair which is biased for read operation, when selected, by a tail circuit which conducts from the respective common node a substantially constant current and which results in a voltage of the common node which is low enough to turn on at least one of the transistors of the differential transistor pair.

22. An integrated circuit as in claim 21 wherein the tail circuit is capable of driving the common node below ground, if necessary, to turn on at least one of the transistors of the differential transistor pair.

23. An integrated circuit as in claim 20 wherein:

the differential transistor pair within each of the first plurality of read amplifiers includes a switching transistor coupling the common source node of the respective differential pair to a first particular node in common with the remaining ones of the first plurality of read amplifiers; and

the differential transistor pair within each of the second plurality of read amplifiers includes a switching transistor coupling the common source node of the respective differential pair to a second particular node in common with the remaining ones of the second plurality of read amplifiers.

24. An integrated circuit as in claim 23 wherein the first and second particular nodes are each coupled to a ground node through a respective transistor configured as a current source.

25. An integrated circuit as in claim 23 wherein the first and second particular nodes are each coupled to a respective capacitive circuit configured to drive the respective particular node to a negative voltage, if necessary, to achieve conduction through at least one transistor of the differential transistor pair within a selected read amplifier associated with the respective particular node.

26. An integrated circuit as in claim 25 wherein the first and second capacitive circuits are each configured as a virtual current source to a negative voltage.

27. An integrated circuit as in claim 16 wherein the pair of complementary input nodes of each respective one of the first and second plurality of read amplifiers are respectively coupled directly to the true and complement bit lines of a respective one of the first and second plurality of bit line pairs.

28. An integrated circuit as in claim 16 wherein the first complementary pair of global bus lines is implemented in an interconnect layer traversing generally overhead of the first plurality of true and complement bit line pairs.

29. An integrated circuit as in claim 28 further comprising:

a global input bus line implemented in the same layer as, and located between, the first complementary pair of global bus lines.

30. An integrated circuit as in claim 28 further comprising:

two other interconnect lines implemented parallel to, in the same interconnect layer, and respectively located on either side of, the first complementary pair of global bus lines;

wherein the two other interconnect lines are voltage quiescent when the corresponding differential signal is driven onto the first complementary pair of global bus lines.

31. An integrated circuit as in claim 30 wherein the first complementary pair of global bus lines is implemented in the topmost interconnect layer.

32. An integrated circuit as in claim 30 wherein at least one of the two other interconnect lines is a power bus line.

33. An integrated circuit as in claim 30 wherein at least one of the two other interconnect lines is a global input bus line.

34. An integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, said integrated circuit comprising:

a first array block including a first plurality of true and complement bit line pairs;

a first plurality of bit line sense amplifiers, each coupled to a respective one of the first plurality of bit line pairs, for sensing a differential signal on the respective bit line pair corresponding to a voltage level previously stored within a respective memory cell of the respective bit line pair which respective memory cell is enabled by a selected word line, and for restoring a voltage level corresponding to the previously stored voltage level into the respective memory cell;

a first complementary pair of local bus lines associated with the first plurality of bit line pairs;

a first plurality of circuit blocks, each coupled to receive on a respective pair of complementary input nodes thereof a differential signal associated with a respective one of the first plurality of bit line pairs and, when enabled, to provide a corresponding differential signal onto the first complementary pair of local bus lines;

a first complementary pair of global bus lines associated with the first plurality of bit line pairs; and

a first bus line amplifier located in close physical proximity to the first plurality of bit line sense amplifiers and arranged to receive on a first pair of complementary input nodes thereof the corresponding differential signal on the first complementary pair of local bus lines and, when enabled, to drive a corresponding differential signal onto the first complementary pair of global bus lines.

35. An integrated circuit as in claim 34 further comprising a processor.

36. An integrated circuit as in claim 34 wherein the first complementary pair of local bus lines is arranged orthogonal to each of the first plurality of bit line pairs.

37. An integrated circuit as in claim 34 wherein:

the first complementary pair of global bus lines is arranged parallel to each of the first plurality of bit line pairs; and

the first complementary pair of global bus lines is further coupled to a plurality of other bus line amplifiers each associated with a respective plurality of bit lines located within respective array blocks other than the first array block.

38. An integrated circuit as in claim 34 wherein:

the first complementary pair of global bus lines is arranged parallel to each of the first plurality of bit line pairs; and

the first complementary pair of global bus lines is further coupled to another bus line amplifier associated with another plurality of bit lines located within the first array block.

39. An integrated circuit as in claim 34 wherein:

the first complementary pair of global bus lines is arranged perpendicular to each of the first plurality of bit line pairs; and

the first complementary pair of global bus lines is further coupled to a plurality of other bus line amplifiers each associated with a respective plurality of other bit lines located within the first array block.

40. An integrated circuit as in claim 34 wherein the first complementary pair of global bus lines is arranged parallel to the first complementary pair of local bus lines.

41. An integrated circuit as in claim 34 further comprising:

a second plurality of true and complement bit line pairs within the first array block located substantially adjacent to the first plurality of true and complement bit line pairs;

a second plurality of bit line sense amplifiers, each coupled to a respective one of the second plurality of bit line pairs, for sensing a differential signal on the respective bit line pair corresponding to a voltage level previously stored within a respective memory cell of the respective bit line pair which respective memory cell is enabled by the selected word line, and for restoring a voltage level corresponding to the previously stored voltage level into the respective memory cell;

a second complementary pair of local bus lines associated with each of the second plurality of bit line pairs;

a second plurality of circuit blocks, each coupled to receive on a respective pair of complementary input nodes thereof a differential signal associated with a respective one of the second plurality of bit line pairs and, when enabled, to provide a corresponding differential signal onto the second complementary pair of local bus lines;

wherein the first complementary pair of global bus lines is also associated with the second plurality of bit line pairs; and

wherein the first bus line amplifier is also located in close physical proximity to the second plurality of bit line sense amplifiers and is arranged to receive on a second pair of complementary input nodes thereof the corresponding differential signal on the second complementary pair of local bus lines and, when enabled, to drive a corresponding differential signal onto the first complementary pair of global bus lines.

42. An integrated circuit as in claim 41 wherein the first bus line amplifier includes provision to select between its first pair of complementary input nodes and its second pair of complementary input nodes.

43. An integrated circuit as in claim 41 wherein:

the first bus line amplifier is generally located between the first plurality of circuit blocks and the second plurality of circuit blocks.

44. An integrated circuit as in claim 34 wherein:

the first bus line amplifier is generally located in line with a group of word line straps for certain word lines within the first array block.

45. An integrated circuit as in claim 34 wherein each of the first plurality of bit line sense amplifiers includes:

a true internal sense amplifier node and a complement internal sense amplifier node, together forming a complementary pair of internal sense amplifier nodes; and

a first pair of transistors respectively coupling the true and complement internal sense amplifier nodes to the true and complement bit lines of the respective one of the first plurality of bit line pairs.

46. An integrated circuit as in claim 45 wherein each of the first plurality of bit line sense amplifiers includes a second pair of transistors respectively coupling its true and complement internal sense amplifier nodes to true and complement bit lines of a corresponding second pair of bit lines located within an array block adjacent to the first array block.

47. An integrated circuit as in claim 45 wherein:

the pair of complementary input nodes of each respective one of the first plurality of circuit blocks are respectively coupled directly to the complementary pair of internal sense amplifier nodes of the respective one of the first plurality of bit line sense amplifiers.

48. An integrated circuit as in claim 45 wherein the pair of complementary input nodes of each respective one of the first plurality of circuit blocks are respectively coupled directly to the true and complement bit lines of a respective one of the first plurality of bit line pairs.

49. An integrated circuit as in claim 34 wherein:

each of the first plurality of circuit blocks includes a respective enable input; and

each respective enable input is coupled to a respective select signal which occurs, for a selected circuit block, substantially before the first plurality of bit line sense amplifiers begin to latch.

50. An integrated circuit as in claim 49 wherein each respective select signal is responsive to a respective column select signal and occurs, for a selected circuit block, approximately at a time when a selected word line within the first array block is driven active.

51. An integrated circuit as in claim 34 wherein the complementary pair of global bus lines is implemented in an interconnect layer traversing generally overhead of the first plurality of bit line pairs.

52. An integrated circuit as in claim 51 further comprising:

an interconnect line implemented in the same layer as, and located between, the first complementary pair of global bus lines.

53. An integrated circuit as in claim 52 wherein the interconnect line located between the first complementary pair of global bus lines is a global input bus line.

54. An integrated circuit as in claim 51 wherein the first complementary pair of global bus lines is implemented in the topmost interconnect layer.

55. An integrated circuit as in claim 51 further comprising:

two other interconnect lines implemented parallel to, in the same interconnect layer, and respectively located on either side of, the first complementary pair of global bus lines; and

wherein the two other interconnect lines are voltage quiescent when the corresponding differential signal is driven onto the first complementary pair of global bus lines.

56. An integrated circuit as in claim 55 wherein at least one of the two other interconnect lines is a power bus line.

57. An integrated circuit as in claim 55 wherein at least one of the two other interconnect lines is a global input bus line.

58. An integrated circuit as in claim 34 wherein:

each of the first plurality of circuit blocks comprises a differential read amplifier having complementary input nodes.

59. An integrated circuit as in claim 58 wherein each of the read amplifiers is enabled by switching the gate terminal of a single transistor per bit line pair.

60. An integrated circuit as in claim 59 wherein each of the read amplifiers is enabled by also switching the gate terminal of a second transistor associated with the first plurality of true and complement bit line pairs, said second transistor arranged in series with a parallel combination of the respective single transistors for each true and complement bit line of the first plurality of complementary bit line pairs.

61. An integrated circuit as in claim 58 wherein capacitive loading presented by each respective read amplifier'"'"'s complementary input nodes is small relative to a total capacitance of the corresponding bit line pair.

62. An integrated circuit as in claim 58 wherein:

each respective read amplifier comprises a differential transistor pair having a common source node; and

the complementary input nodes of each respective read amplifier comprise respective gate terminals of the differential transistor pair.

63. An integrated circuit as in claim 62 wherein the differential transistor pair of each respective read amplifier comprises an N-channel transistor pair which is biased for read operation, when selected, by a circuit which conducts from the common node a substantially constant current and which results in a voltage of the common node which is low enough to turn on at least one of the transistors of the differential transistor pair.

64. An integrated circuit as in claim 63 wherein the circuit which conducts from each respective common node is capable of driving the common node below ground, if necessary, to turn on at least one of the transistors of the differential transistor pair.

65. An integrated circuit as in claim 62 wherein the differential transistor pair within each read amplifier includes a switching transistor coupling the common source node of the respective differential pair to a particular node in common with the remaining read amplifiers.

66. An integrated circuit as in claim 65 wherein the particular node is directly coupled to a ground node.

67. An integrated circuit as in claim 65 wherein the particular node is coupled to a ground node through a transistor configured as a current source.

68. An integrated circuit as in claim 65 wherein the particular node is coupled to a capacitive circuit configured to drive the particular node to a negative voltage, if necessary, to achieve conduction through at least one transistor of the differential transistor pair within a selected read amplifier associated with the particular node.

69. An integrated circuit as in claim 68 wherein the capacitive circuit is configured as a virtual current source to a negative voltage.

70. An integrated circuit as in claim 34 wherein:

each of the first circuit blocks comprises a pass transistor circuit arranged to communicate, when enabled, the corresponding differential signal associated with the selected one of the first plurality of bit line pairs onto the first complementary pair of local bus lines.

71. An integrated circuit as in claim 70 wherein the first bus line amplifier comprises a two-stage amplifier.

72. An integrated circuit as in claim 70 wherein each of the first plurality of true and complement bit line pairs and the first complementary pair of local bus lines are equilibrated to a particular equilibration voltage which is less than VDD.

73. An integrated circuit as in claim 72 wherein the particular equilibration voltage is approximately equal to one-half of a voltage to which a memory cell is written when restoring an internal high level into the memory cell.

74. An integrated circuit as in claim 72 wherein the first complementary pair of global bus lines is precharged substantially to VDD.

75. An integrated circuit as in claim 70 wherein each pass transistor circuit respectively directly couples its associated true and complement bit line to the true and complement local bus line of the first complementary pair of local bus lines.

76. An integrated circuit as in claim 70 wherein each of the first plurality of bit line sense amplifiers includes:

a true internal sense amplifier node and-a complement internal sense amplifier node, together forming a complementary pair of internal sense amplifier nodes; and

a first pair of transistors respectively coupling the true and complement internal sense amplifier nodes to the true and complement bit lines of the respective one of the first plurality of bit line pairs;

wherein each pass transistor circuit respectively couples the true and complement internal sense amplifier nodes of its associated bit line sense amplifier to the true and complement local bus line of the first complementary pair of local bus lines.

77. An integrated circuit as in claim 70 wherein the first complementary pair of local bus lines comprises a bidirectional pair of local input/output lines.

78. An integrated circuit as in claim 77 further comprising:

a selection circuit for enabling a selected one of the pass transistor circuits;

wherein the selection circuit is responsive at least partially to a column select signal, and turns on the selected one of the pass transistor circuits substantially before the first plurality of bit line sense amplifiers begin to latch;

wherein, during a write cycle, the selection circuit turns off the selected one of the pass transistor circuits approximately at a time when the plurality of bit line sense amplifiers begin to latch; and

wherein, during a read cycle, the selection circuit turns off the selected one of the pass transistor circuits well after the plurality of bit line sense amplifiers begin to latch.

79. In an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, a method of operating the integrated circuit comprising:

enabling a selected word line corresponding to a selected memory cell to cause a differential signal to develop on each pair of bit lines having a memory cell coupled to the selected word line as a result of charge from each such memory cell being shared with its associated true or complement bit line, and to communicate each respective differential signal, as it develops, to a respective bit line sense amplifier;

enabling a read amplifier coupled to a selected complementary pair of bit lines to cause a differential signal to develop on a complementary pair of bus lines separate from the bit line pairs, said read amplifier being separate from the bit line sense amplifiers; and

then

latching the bit line sense amplifiers for all bit line pairs having a memory cell coupled to the selected word line.

80. A method as in claim 79 employed in a dynamic memory array embedded within an integrated processor circuit.

81. A method as in claim 79 wherein the bit line sense amplifier latching step occurs substantially after the read amplifier enabling step.

82. A method as in claim 79 wherein the differential signal begins to develop on the complementary pair of bus lines upon enabling the selected word line.

83. A method as in claim 79 wherein the differential signal is developed to a substantial magnitude on the complementary pair of bus lines before a substantial differential signal is developed on the bit line pairs as a result of latching the bit line sense amplifiers.

84. A method as in claim 79 wherein the differential signal is developed to a substantial magnitude on the complementary pair of bus lines before beginning to latch the bit line sense amplifiers.

85. A method as in claim 84 wherein additional differential signal is developed on the complementary pair of bus lines after beginning to latch the bit line sense amplifiers.

86. In an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, a circuit comprising:

means for enabling a selected word line corresponding to a selected memory cell to cause a differential signal to develop on each pair of bit lines having a memory cell coupled to the selected word line as a result of charge from each such memory cell being shared with its associated true or complement bit line, and to communicate each respective differential signal, as it develops, to a respective bit line sense amplifier;

means for enabling, prior to latching the bit line sense amplifiers, a read amplifier coupled to a selected complementary pair of bit lines and separate from the bit line sense amplifiers, to cause a differential signal to develop on a complementary pair of bus lines separate from the bit lines; and

means for latching the bit line sense amplifiers for all bit lines having a memory cell coupled to the selected word line.

87. A circuit as in claim 86 wherein:

the means for enabling a read amplifier and the means for enabling a selected word line are configured so that the differential signal on the pair of bus lines begins to develop at substantially the same time as the selected word line is enabled.

88. In an integrated circuit including a dynamic memory array having individual memory cells organized as rows and columns, each row corresponding to one of a plurality of word lines and each column corresponding to one of a plurality of true and complement bit line pairs, a memory cell at a given row and column being coupled to the corresponding word line and coupled to either the true or complement corresponding bit line, a method of operating the integrated circuit comprising:

developing on a first bus a first read signal for a selected memory cell prior to latching a bit line sense amplifier coupled to the selected memory cell, said first read signal corresponding to a voltage level previously stored within the selected memory cell; and

developing on a second bus a second read signal corresponding to the first read signal prior to latching the bit line sense amplifier coupled to the selected memory cell, said second read signal thereby corresponding to the voltage level previously stored within the selected memory cell.

89. A method as in claim 88 wherein:

the first bus comprises a complementary pair of local bus lines; and

the second bus comprises a complementary pair of global bus lines.

90. A method as in claim 88 wherein the first signal developing step includes:

enabling a pass transistor circuit to couple at least indirectly a bit line corresponding to the selected memory cell to the first bus prior to latching a bit line sense amplifier coupled to the selected memory cell.

91. A method as in claim 88 wherein the first signal developing step includes:

enabling an amplifier circuit having an input coupled at least indirectly to a bit line corresponding to the selected memory cell and having an output coupled to the first bus, prior to latching a bit line sense amplifier coupled to the selected memory cell.