Forward-link traffic/paging-channel interleaving for communication systems based on closed-form expressions
First Claim
Patent Images
1. A method for interleaving a forward-link paging or traffic channel of a communication system, comprising the steps of:
- (a) receiving an un-interleaved symbol stream for the forward-link channel;
(b) implementing a closed-form expression relating each un-interleaved symbol position to a corresponding interleaved symbol position to generate an interleaved symbol position for each symbol in the un-interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each un-interleaved symbol position to generate bits in a binary value representing a corresponding interleaved symbol position; and
(c) generating an interleaved symbol stream from the un-interleaved symbol stream using the interleaved symbol positions.
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Abstract
Interleaving of forward-link paging or traffic channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For each cdmaOne forward-link paging or traffic channel, the closed-form expression relates each un-interleaved symbol position to a corresponding interleaved symbol position, which is used to generate an interleaved symbol stream from the un-interleaved symbol stream. In one hardware implementation, the forward-link interleaver of the present invention has an address generation unit made from a modulo counter, a multiplier, and an adder.
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Citations
21 Claims
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1. A method for interleaving a forward-link paging or traffic channel of a communication system, comprising the steps of:
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(a) receiving an un-interleaved symbol stream for the forward-link channel;
(b) implementing a closed-form expression relating each un-interleaved symbol position to a corresponding interleaved symbol position to generate an interleaved symbol position for each symbol in the un-interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each un-interleaved symbol position to generate bits in a binary value representing a corresponding interleaved symbol position; and
(c) generating an interleaved symbol stream from the un-interleaved symbol stream using the interleaved symbol positions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 19)
the closed-form expression is given by;
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3. The method of claim 2, wherein the closed-form expression is implemented in software.
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4. The method of claim 2, wherein the closed-form expression is implemented in hardware.
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5. The method of claim 4, wherein the closed-form expression is implemented in a single integrated circuit.
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6. The method of claim 5, wherein the hardware implementation comprises:
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(1) a modulo-384 or higher counter adapted to generate the 9-tuple (c8, c7, c6, c5, c4, c3, c2, c1, c0) from the un-interleaved symbol position;
(2) a bit reversal unit adapted to generate the 6-tuple ( e5, e4, e3, e2, e1, e0) from the 6-tuple (c5, c4, c3, c2, c1, c0) by reversing the order of the bits;
(3) a multiply-by-6 block adapted to multiply the value corresponding to the 6-tuple (e5, e4, e3, e2, e1, e0) by 6; and
(4) an adder to add the value corresponding to the 3-tuple (c8, c7, c6) and the value generated by the multiply-by-6 block to generate the interleaved symbol position.
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7. The method of claim 5, wherein the closed-form expression is implemented using a circuit of logic devices corresponding to the following relationships:
-
where “
⊕
”
represents the logical “
XOR”
function, “
·
”
represents the logical “
AND”
function, and “
+”
represents the logical “
OR”
function.
-
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19. The method of claim 1, wherein the closed-form expression is implementable without relying on any lookup tables.
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8. An interleaver for interleaving a forward-link paging or traffic channel of a communication system, comprising:
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(a) means for receiving an un-interleaved symbol stream for the forward-link channel;
(b) means for implementing a closed-form expression relating each un-interleaved symbol position to a corresponding interleaved symbol position to generate an interleaved symbol position for each symbol in the un-interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each un-interleaved symbol position to generate bits in a binary value representing a corresponding interleaved symbol position; and
(c) means for generating an interleaved symbol stream from the un-interleaved symbol stream using the interleaved symbol positions. - View Dependent Claims (9, 10, 11, 12, 13, 14, 20)
the closed-form expression is given by;
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10. The interleaver of claim 9, wherein the closed-form expression is implemented in software.
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11. The interleaver of claim 9, wherein the closed-form expression is implemented in hardware.
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12. The interleaver of claim 11, wherein the closed-form expression is implemented in a single integrated circuit.
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13. The interleaver of claim 12, wherein the hardware implementation comprises:
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(1) a modulo-384 or higher counter adapted to generate the 9-tuple (c8, c7, c6, c5, c4, c3, c2, c1, c0) from the un-interleaved symbol position;
(2) a bit reversal unit adapted to generate the 6-tuple (e5, e4, e3, e2, e1, e0) from the 6-tuple (c5, c4, c3, c2, c1, c0) by reversing the order of the bits;
(3) a multiply-by-6block adapted to multiply the value corresponding to the 6-tuple (e5, e4, e3, e2, e1, e0) by 6; and
(4) an adder to add the value corresponding to the 3-tuple (c8, c7, c6) and the value generated by the multiply-by-6 block to generate the interleaved symbol position.
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14. The interleaver of claim 12, wherein the closed-form expression is implemented using a circuit of logic devices corresponding to the following relationships:
-
where “
⊕
”
represents the logical “
XOR”
function, “
·
”
represents the logical “
AND”
function, and “
+”
represents the logical “
OR”
function.
-
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20. The interleaver of claim 8, wherein the closed-form expression is implementable without relying on any lookup tables.
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15. An integrated circuit having an interleaver for interleaving a forward-link paging or traffic channel of a communication system, wherein the interleaver comprises:
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(A) a symbol buffer; and
(B) an address generation unit adapted to generate symbol addresses for reading un-interleaved symbols from or writing interleaved symbols to the symbol buffer, wherein the address generation unit implements a closed-form expression relating each un-interleaved symbol position to a corresponding interleaved symbol position to generate an interleaved symbol position for each symbol in the un-interleaved symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each un-interleaved symbol position to generate bits in a binary value representing a corresponding interleaved symbol position. - View Dependent Claims (16, 17, 18, 21)
the closed-form expression is given by;
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17. The integrated circuit of claim 16, wherein the address generation unit comprises:
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(1) a modulo-384 or higher counter adapted to generate the 9-tuple (c8, c7, c6, c5, c4, c3, c2, c1, c0) from the un-interleaved symbol position;
(2) a bit reversal unit adapted to generate the 6-tuple (e5, e4, e3, e2, e1, e0) from the 6-tuple (c5, c4, c3, c2, c1, c0) by reversing the order of the bits;
(3) a multiply-by-6 block adapted to multiply the value corresponding to the 6-tuple (e5, e4, e3, e2, e1, e0) by 6; and
(4) an adder to add the value corresponding to the 3-tuple (c8, c7, C6) and the value generated by the multiply-by-6 block to generate the interleaved symbol position.
-
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18. The integrated circuit of claim 16, wherein the closed-form expression is implemented using a circuit of logic devices corresponding to the following relationships:
-
where “
⊕
”
represents the logical “
XOR”
function, “
·
”
represents the logical “
AND”
function, and “
+”
represents the logical “
OR”
function.
-
-
21. The integrated circuit of claim 15, wherein the closed-form expression is implementable without relying on any lookup tables.
Specification
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Current AssigneeAvago Technologies General IP PTE Limited (Broadcom, Inc.)
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Original AssigneeLucent Technologies, Inc. (Nokia Corporation)
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InventorsPrasad, Mohit K.
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Primary Examiner(s)Ton, Dang
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Assistant Examiner(s)TON, ANTHONY T
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Application NumberUS09/039,158Time in Patent Office1,089 DaysField of Search370/335, 370/441, 370/332, 370/442, 370/295, 370/331, 370/203, 370/320, 370/209, 370/330, 370/311, 370/480, 370/204, 370/355, 370/342, 370/341, 370/350, 370/501, 455/428, 455/449, 455/447, 455/456, 455/522, 455/422, 714/2, 375/130, 375/134, 375/137US Class Current370/335CPC Class CodesH03M 13/271 Row-column interleaver with...H03M 13/2764 Circuits thereforeH04L 1/0043 Realisations of complexity ...H04L 1/0071 Use of interleaving interle...
