Forward-link sync-channel interleaving/de-interleaving for communication systems based on closed-form expressions

• US 6,198,733 B1
• Filed: 03/13/1998
• Issued: 03/06/2001
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Prasad, Mohit K.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): HOM, SHICK C
• Application Number:
  US09/039,154
• Time in Patent Office: 1,089 Days
• Field of Search: 370/210, 370/342, 370/350, 370/441, 370/487, 370/503, 370/320, 370/479, 375/140, 375/142, 375/143, 375/145, 375/149, 375/150, 375/152, 375/262, 375/295, 375/372, 375/316
• US Class Current: 370/342
• CPC Class Codes: H03M 13/271 Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
• CPC Class Codes: H03M 13/2764 Circuits therefore
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

Interleaving and de-interleaving of forward-link Sync channels is performed by implementing closed-form expressions that are equivalent to the table-based processing specified in the cdmaOne telecommunication specification. The implementation can be in either hardware or software or a combination of both. For Sync-channel interleaving, the closed-form expression relates each un-interleaved symbol position to a corresponding interleaved symbol position, which is used to generate an interleaved symbol stream from the un-interleaved symbol stream. For Sync-channel de-interleaving, the closed-form expression relates each interleaved symbol position to a corresponding de-interleaved symbol position, which is used to generate a de-interleaved symbol stream from the interleaved symbol stream. In one hardware implementation, the forward-link interleaver/de-interleaver of the present invention has an address generation unit made from a modulo counter and a bit reversal unit.

Claims

1. A method for interleaving/de-interleaving a forward-line Sync channel of a communication system, comprising the steps of:

(a) receiving an input symbol stream for the forward-link Sync channel;

(b) implementing a closed-form expression relating each input symbol position to an output symbol position to generate the output symbol position for each symbol in the input symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each input symbol position to generate bits in a binary value representing a corresponding output symbol position; and

(c) generating an output symbol stream from the input symbol stream using the generated output symbol positions, wherein;

when interleaving, the input symbol stream is an un-interleaved symbol stream and the output symbol stream is an interleaved symbol stream; and

when de-interleaving, the input symbol stream is an interleaved symbol stream and the output symbol stream is a de-interleaved symbol stream.

2. The method of claim 1, wherein:

the closed-form expression is given by;

3. The method of claim 2, wherein the closed-form expression is implemented in software.

4. The method of claim 2, wherein the closed-form expression is implemented in hardware.

5. The method of claim 4, wherein the closed-form expression is implemented in a single integrated circuit.

6. The method of claim 5, wherein the hardware implementation comprises:

(1) a modulo-128 or higher counter adapted to generate the 7-tuple (c₆, c₅, c₄, c₃, c₂, c₁, c₀) for the input symbol position; and

(2) a bit reversal unit adapted to generate the 7-tuple (c₀, c₁, c₂, c₃, c₄, c₅, c₆) for the output symbol position from the input symbol position.

7. The method of claim 6, wherein the hardware implementation further comprises a two-input mux adapted to receive the input symbol position, the output symbol position, and a control signal that determines whether the input symbol position or the output symbol position is presented at the output of the mux.

19. The method of claim 1, wherein the closed-form expression is implementable without relying on any lookup tables.

8. An apparatus for interleaving/de-interleaving a forward-link Sync channel of a communication system, comprising:

(a) means for receiving an input symbol stream for the forward-link Sync channel;

(b) means for implementing a closed-form expression relating each input symbol position to an output symbol position to generate the output symbol position for each symbol in the input symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each input symbol position to generate bits in a binary value representing a corresponding output symbol position; and

(c) means for generating an output symbol stream from the input symbol stream using the output symbol positions, wherein;

when interleaving, the input symbol stream is an un-interleaved symbol stream and the output symbol stream is an interleaved symbol stream; and

when de-interleaving, the input symbol stream is an interleaved symbol stream and the output symbol stream is a de-interleaved symbol stream.

9. The apparatus of claim 8, wherein:

the closed-form expression is given by;

10. The apparatus of claim 9, wherein the closed-form expression is implemented in software.

11. The apparatus of claim 9, wherein the closed-form expression is implemented in hardware.

12. The apparatus of claim 11, wherein the closed-form expression is implemented in a single integrated circuit.

13. The apparatus of claim 12, wherein the hardware implementation comprises:

(1) a modulo-128 or higher counter adapted to generate the 7-tuple (c₆, c₅, c₄, c₃, c₂, c₁, c₀) for the input symbol position; and

(2) a bit reversal unit adapted to generate the 7-tuple (c₀, c₁, c₂, c₃, c₄, c₅, c₆) for the output symbol position from the input symbol position.

14. The apparatus of claim 13, wherein the hardware implementation further comprises a two-input mux adapted to receive the input symbol position, the output symbol position, and a control signal that determines whether the input symbol position or the output symbol position is presented at the output of the mux.

20. The apparatus of claim 8, wherein the closed-form expression is implementable without relying on any lookup tables.

15. An integrated circuit having an interleaver/de-interleaver for processing a forward-link Sync channel of a communication system, wherein the interleaver/de-interleaver comprises:

(A) a symbol buffer; and

(B) an address generation unit adapted to generate symbol addresses for reading data from or writing data to the symbol buffer, wherein the address generation unit implements a closed-form expression relating each input symbol position of an input symbol stream to an output symbol position of an output symbol stream to generate the output symbol position for each symbol in the input symbol stream, wherein the closed-form expression corresponds to two or more different sets of mathematical operations being applied to bits in a binary value representing each input symbol position to generate bits in a binary value representing a corresponding output symbol position, wherein;

when interleaving, the input symbol stream is an un-interleaved symbol stream and the output symbol stream is an interleaved symbol stream; and

when de-interleaving, the input symbol stream is an interleaved symbol stream and the output symbol stream is a de-interleaved symbol stream.

16. The integrated circuit of claim 15, wherein:

the closed-form expression is given by;

17. The integrated circuit of claim 16, wherein the address generation unit comprises:

(1) a modulo-128 or higher counter adapted to generate a 7-tuple (c₆, c₅, c₄, c₃, c₂, c₁, c₀) for the input symbol position; and

(2) a bit reversal unit adapted to generate the 7-tuple (c₀, c₁, c₂, c₃, c₄, c₅, c₆) for the output symbol position from the input symbol position.

18. The integrated circuit of claim 17, wherein the address generation unit further comprises a two-input mux adapted to receive the input symbol position, the output symbol position, and a control signal that determines whether the input symbol position or the output symbol position is presented at the output of the mux.

21. The integrated circuit of claim 15, wherein the closed-form expression is implementable without relying on any lookup tables.