Feher keying (KF) modualtion and transceivers including clock shaping processors

• US 6,198,777 B1
• Filed: 08/30/1999
• Issued: 03/06/2001
• Est. Priority Date: 08/31/1998
• Status: Expired due to Term

• Current Assignee: Kamilo Feher
• Original Assignee: Kamilo Feher
• Inventors: Feher, Kamilo
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US09/385,693
• Time in Patent Office: 554 Days
• Field of Search: 375/216, 375/238, 375/259, 375/295, 375/360, 327/100, 327/124, 327/143, 327/144, 327/145
• US Class Current: 375/295
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 27/00 Modulated-carrier systems
• CPC Class Codes: H04L 27/0004 using wavelets
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence
• CPC Class Codes: H04L 27/2637 with direct modulation of individual subcarriers
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

Ultra high spectral efficient Feher Keying (FK) Modulation and Demodulation (Modem), Baseband Processing (BBP), Intermediate Frequency (IF) and Radio Frequency (RF) signal generation and processing methods and implementations, including Clock Modulated (CM) and Shaped Clocked (SC) Transmitters-Receivers (transceivers) are disclosed. Additional embodiments, including Feher Quadrature Shift Keying (FQPSK) and Feher Quadrature Modulation (FQAM), in conjunction with CM and SC are also described. In the FK modulator, specified clock converted and clock shaped signal parameters are generated. These are based on the input data signal patterns and are generated by means of control signals, which are designed in the data input signal interface data signal and/or clock signal encoder units. The selectable clock signal parameters include symmetrical and non-symmetrical clock signals, shaped band-limited continuous clock signal patterns, shaped encoded clock signals, variable rise and fall time clock signals, clock signals having adjustable on and off duration, multilevel and shaped clock signals and asynchronous clock signal information transmission means, where asynchronous clocking is referenced to the incoming data source signals. The FK processors are also used in conjunction with cross-correlated FQPSK quadrature and also non quadrature modem systems as input drive signals to FM VCO based systems to SSB to VSB to DSB-SC to QAM, and FQAM and to coded systems with adaptive equalized receivers, Non Redundant Error Correction (NEC), pseudo-error monitor systems. The FK systems and FT apparatus comprises entire transceiver structures including LIN (linear) and NLA (Non Linear Amplifier) transmitter receiver, AGC, synchronization and demodulation and post demodulation signal processors.

Claims

1. A structure comprising:

a splitter receiving an input signal and splitting said input signal into a plurality of signal streams;

a clock generator receiving one of said plurality of signal streams and generating a clock signal;

at least one shaped clock generator means receiving said clock signal and generating at least one shaped clock signal;

a set of input ports for receiving said at least one shaped clock signal;

a selector switch for selecting a particular one of the shaped clock signals, said selector switch having a first input interface port coupled to receive data-based selection control signals, and a set of input ports coupled to the shaped clock signals; and

an output interface port coupled to said selector switch output.

2. A system architecture for use with a transmitter, said system architecture comprising:

a data input interface for receiving input data and for generating an input data based clock selector signal;

a plurality of input ports for receiving a plurality of clock signals including shaped clock signals and unshaped clock signals;

a set of one or more clock generators generating processed clock signals at least some of which processed clock signals differing from each other in one or more clock parameters;

a selector switch for selecting a particular one of said processed clock signals; and

a data interface output port for receiving said selected processed clock signal and communicating it to said transmitter.

3. An architecture comprising:

a data interface input for receiving input data and for providing an input data-based clock selector data signal;

a set of input ports for receiving a set of shaped clock signals and of not-shaped clock signals;

a set of one or more clock generators which differ from each other in one or more clock parameters;

a selector switch for selecting one of the processed clock signals; and

a data interface output port for receiving said selected signal and providing it to the transmitter circuitry.