Communication link with isochronous and asynchronous priority modes

• US 6,199,132 B1
• Filed: 06/17/1998
• Issued: 03/06/2001
• Est. Priority Date: 06/17/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hewitt, Larry D., Gulick, Dale E.
• Primary Examiner(s): An, Meng-Ai T.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/098,854
• Time in Patent Office: 993 Days
• Field of Search: 712/1, 710/113, 710/116, 710/107, 710/106
• US Class Current: 710/107
• CPC Class Codes: G06F 13/4213 with asynchronous protocol

Abstract

A bus transfers information including isochronous and asynchronous data between a first and a second integrated circuit. The bus guarantees a minimum bandwidth to isochronous data and also tries to minimize latency for isochronous data. The bus transfers data in asynchronous priority mode during a first portion of a first time period, wherein asynchronous data is transferred preferentially over isochronous data. Transfers over the bus selectably switch to isochronous priority mode for a second portion of the first time period in order to guarantee transfer of a predetermined amount of isochronous data during the first time period, thus guaranteeing the minimum bandwidth to isochronous data.

Claims

1. A method of transferring information on a bus between a first and a second integrated circuit, the information including address information, isochronous data, asynchronous data and control information, the method comprising:

transferring data on the bus in asynchronous priority mode during a first portion of a first time period, wherein during asynchronous priority mode, asynchronous data has priority over isochronous data for transfers on the bus; and

selectably switching to isochronous priority mode for a second portion of the first time period to guarantee transfer of a predetermined amount of isochronous data during the first time period.

2. The method as recited in claim 1 wherein the first portion includes the beginning of the first time period.

3. The method as recited in claim 1 wherein no asynchronous data is transferred during isochronous priority mode.

4. The method as recited in claim 3 wherein isochronous data is transferred during asynchronous priority mode.

5. The method as recited in claim 1 wherein the predetermined amount of isochronous data is the maximum amount of isochronous data that can be transferred during the first time period over the bus.

6. The method as recited in claim 1 wherein the predetermined amount of isochronous data is the actual amount of isochronous data that is requested to be transferred during the first time period.

7. The method as recited in claim 1, further comprising:

after switching to isochronous priority mode, switching back to asynchronous priority mode for a third portion of the first time period, the third portion occurring after all isochronous data transfers for the first time period are completed.

8. The method as recited in claim 1 wherein each of the integrated circuits includes a plurality of request circuits requesting to transfer data across the bus, each integrated circuit including at least one isochronous request circuit and at least one asynchronous request circuit.

9. The method as recited in claim 1 wherein the determining comprises:

keep track of an amount of isochronous data transferred during the first time period;

keep track of an amount of time remaining in the first time period;

switching to isochronous priority mode according to the time remaining in the first period, the predetermined amount of isochronous data to be transferred and the amount of isochronous data transferred so far in the first time period, to guarantee that at least the predetermined amount of isochronous data may be transferred during the first time period.

10. The method as recited in claim 1 wherein switching to isochronous priority mode occurs when any integrated circuit coupled to the bus wants to switch to isochronous priority mode and transmits a control message on the bus indicative thereof.

11. The method as recited in claim 1 further comprising:

determining in a local-request arbiter which of a plurality of requesters in the first integrated circuit will send data on the bus during the first time period, with at least one of the requesters being isochronous and at least one of the requesters being asynchronous, according to whether the bus is in isochronous or asynchronous priority mode.

12. The method as recited in claim 1 further comprising halting transfer of an asynchronous block of data when entering isochronous priority mode.

13. The method as recited in claim 1 further comprising:

halting transfer in the middle of an isochronous block of data when in asynchronous priority mode and a request is made to transfer an asynchronous block of data; and

transferring the asynchronous block of data after halting the isochronous block of data.

14. The method as recited in claim 1 wherein a bus message having control information is sent during isochronous priority mode.

15. The method according to claim 1 wherein selectably switching includes determining whether an amount of time remaining in the first time period is greater than a transfer time required to guarantee transfer of the predetermined amount of isochronous data during the first time period.

16. The method as recited in claim 15 wherein the bus remains in asynchronous priority mode if it is determined that the amount of time remaining in the first time period is greater than the transfer time.

17. An apparatus comprising:

a bus interface coupled to transfer information to and from a bus, the information including address information, isochronous data, asynchronous data and control information, the bus interface including, an arbiter circuit responsive to a priority mode of the bus to selectably transfer one of asynchronous and isochronous data over the bus, the arbiter determining a priority mode of the bus to be asynchronous priority mode during a first portion of a predetermined time period on the bus, the arbiter guaranteeing transfer of a predetermined amount of isochronous data by selectably switching to isochronous priority mode for a second portion of the first time period, wherein

during asynchronous priority mode, asynchronous data transfers are preferentially selected over isochronous transfers and wherein during isochronous priority mode isochronous data transfers are preferentially selected over asynchronous transfers.

18. The apparatus as recited in claim 17 wherein the arbiter circuit is further responsive to control information received over the bus to enter isochronous priority mode.

19. The apparatus as recited in claim 17 further comprising a plurality of channels, each channel coupled to the bus interface and a respective one of a plurality of functional circuits, and wherein a first of said channels processes asynchronous data and a second of said channels processes isochronous data, the first and second channels being coupled to respectively provide an asynchronous request and an isochronous request to the arbiter circuit to transfer data across the bus.

20. The apparatus as recited in claim 17 wherein the bus interface comprises:

a first receive controller, coupled to receive from the bus a first clock signal, a first control signal and at least a first receive data signal, the first control and receive data signal being received synchronously with said first clock signal; and

a first transmit controller, coupled to provide the bus a second clock signal, a second control signal and at least a second data signal, the second control and the second data signal being provided synchronously with said second clock signal.

21. The apparatus as recited in claim 19 wherein each of the channels includes at least one of a transmit and receive buffer, the transmit and receive buffers storing a plurality of data for transmitting to and receiving from the bus.

22. The apparatus as recited in claim 21 wherein the transmit and receive buffers are implemented as first-in-first out (FIFO) buffers.

23. The apparatus as recited in claim 17 wherein the first portion includes the beginning of the first time period.

24. The apparatus as recited in claim 17 wherein the arbiter circuit selects no asynchronous data for transfer during isochronous priority mode.

25. The apparatus as recited in claim 24 wherein isochronous data is selected by the arbiter circuit for transfer during asynchronous priority mode if no asynchronous requests are presented in the arbiter circuit.

26. The apparatus as recited in claim 17 wherein the predetermined amount of isochronous data is the maximum amount of isochronous data that can be transferred during the first time period over the bus.

27. The apparatus as recited in claim 17 wherein the predetermined amount of isochronous data is the actual amount of isochronous data that is requested to be transferred during the first time period by the channels.

28. The apparatus as recited in claim 17, wherein the arbiter circuit is responsive to completion of all isochronous data transfers for the first time period to switch back to asynchronous priority mode for a third portion of the first time period.

29. The apparatus as recited in claim 17 wherein the arbiter circuit further comprises:

a first counter for tracking an amount of isochronous data transferred during the first time period;

a second counter for tracking an amount of time left in the first time period; and

wherein

the arbiter circuit is responsive to switch to isochronous priority mode according to the time remaining in the first time period, the predetermined amount of isochronous data to be transferred and the amount of isochronous data transferred so far, thereby guaranteeing that at least the predetermined amount of isochronous data is transferred during the first time period.

30. The apparatus as recited in claim 17 wherein the arbiter circuit provides control information to the bus when the arbiter circuit makes a determination to enter isochronous priority mode, the control information indicative of the determination to enter isochronous priority mode.

31. The apparatus as recited in claim 17 wherein the arbiter circuit halts transfer of an asynchronous block of data when entering isochronous priority mode.

32. The apparatus as recited in claim 17 wherein the arbiter circuit halts transfer in the middle of an isochronous block of data when in asynchronous priority mode and a request is made to transfer an asynchronous block of data.

33. The apparatus as recited in claim 19 wherein the arbiter circuit is disposed on a processor module, the processor module further including a central processing unit and system memory, the central processing unit and system memory each being one of the functional circuits.

34. The apparatus as recited in claim 33 further comprising an interface module coupled to the bus, the interface module including a second bus interface and a second arbiter circuit, and an additional plurality of channels coupled to the second arbiter circuit and an additional plurality of functional circuits respectively coupled to the additional plurality of channels.

35. An apparatus comprising:

means for transmitting and receiving information on a bus, the information including address information, isochronous data, asynchronous data and control information;

means for transmitting information on the bus in asynchronous priority mode during a first portion of a first time period, wherein during asynchronous priority mode asynchronous data has priority over isochronous data for transfers on the bus; and

means for selectably switching to isochronous priority mode for a second portion of the first time period to guarantee transfer of a predetermined amount of isochronous data during the first time period.

36. The apparatus as recited in claim 35 wherein the first portion includes the beginning of the first time period.

37. The apparatus as recited in claim 35 wherein no asynchronous data is transferred during isochronous priority mode.

38. The apparatus as recited in claim 37 wherein isochronous data is transferred during asynchronous priority mode.