Management communication bus for networking devices

• US 6,199,133 B1
• Filed: 03/29/1996
• Issued: 03/06/2001
• Est. Priority Date: 03/29/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Schnell, Arnold Thomas
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): DHARIA, RUPAL
• Application Number:
  US08/624,176
• Time in Patent Office: 1,803 Days
• Field of Search: 395/259, 395/290, 395/293, 395/200.05, 395/285, 395/474, 395/476, 395/325, 710/109, 710/110, 710/113, 710/105, 710/129, 709/208, 712/20
• US Class Current: 710/110
• CPC Class Codes: H04L 41/24 using dedicated network management hardware

Abstract

A management communication bus for enabling management of network devices in a network system. The network system includes at least one bus master device and at least one slave device, where the bus master and slave devices are distributed within the network devices. Each network device includes a slave device or a bus master device or both. The bus includes several conductors for state signals for defining four states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to the address. The bus further includes several conductors for data signals for transferring information data depending upon the different states, where the information data includes bus request, slave identification, the address and the data corresponding to the address. Each bus master includes an interface to the bus to step through each of the states for controlling each cycle. Each bus master and slave device includes an identification number with a predetermined priority.

Claims

1. A management communication bus for a plurality of network devices of a network system, the network system including at least one bus master device and at least one slave device, said management communication bus comprising:

a number of encoded bus state signals incorporated on the management communication bus, where said number is greater than one, that collectively define more than said number of bus states including bus states for arbitration, for slave identification, for asserting an address and for asserting data corresponding to said address;

a plurality of bus data signals, incorporated on the management communication bus, for transferring information data depending upon said bus states, said information data including bus request, slave identification, said address and said data; and

each bus data signal within said plurality of bus data signals has a definition, at least one of said definitions is operable to be redefined during a change of at least one of said number of bus states.

2. The management communication bus of claim 1, further comprising:

a bus clock signal for synchronizing bus state transitions.

3. The management communication bus of claim 2, wherein said bus clock signal has a frequency of approximately eight megahertz.

4. The management communication bus of claim 1, wherein said number of encoded bus state signals includes at least two bus state signals that collectively define at least four bus states, said four bus states including first and second address states for asserting first and second address portions of said address, respectively.

5. The management communication bus of claim 4, wherein a bus master device asserts a cycle definition signal on one of said plurality of bus data signals during one of said first and second address states indicating whether the operation is a read cycle and whether the operation is a write cycle.

6. The management communication bus of claim 4, wherein said plurality of bus data signals includes at least eight data signals.

7. The management communication bus of claim 4, wherein a slave device asserts a busy signal on one of said plurality of bus data signals to indicate that the slave device is busy during said second address state, and wherein said management communication bus stays in said second address state until the slave device deasserts said busy signal.

8. The management communication bus of claim 1, wherein said number of encoded bus state signals includes only two bus state signals and wherein said bus data signals includes eight data signals for a total of ten bus signals.

9. The management communication bus of claim 1, wherein only one of said number of encoded bus state signals transitions at a time between consecutive bus states of said more than said number of bus states.

10. A management communication bus system, comprising:

a bus, including;

a number of encoded bus state signals, where said number is greater than one, that collectively define more than said number of bus states including a first bus state for arbitration and slave device identification, a second bus state for asserting an address and a third bus state for asserting data corresponding to said address; and

a plurality of bus data signals for transferring information data depending upon said bus states, said information data including bus request and slave identification information during said first bus state, said address during said second bus state and said data during said third bus state;

at least one bus master device coupled to said bus; and

at least one slave device coupled to said bus.

11. The management communication bus system of claim 10, wherein said number of encoded bus state signals collectively define at least four bus states wherein said second bus state includes first and second address states for asserting first and second address portions, respectively.

12. The management communication bus system of claim 10, wherein:

said at least one bus master device includes an interface for asserting said number of encoded bus state signals to transition between said more than said number of bus states; and

wherein said bus master interface asserts said plurality of bus state signals and a bus data signal to initiate a first bus state to gain control of said bus and asserts said plurality of bus data signals to identify said at least one slave device, asserts said number of encoded bus state signals to advance to a second bus state and asserts said address on said plurality of bus data signals and asserts said number of encoded bus state signals to advance to a third bus state to perform a data cycle.

13. The management communication bus system of claim 12, wherein said bus master interface asserts a cycle definition signal during said second bus state indicating the direction of said data between said at least one bus master device and said at least one slave device.

14. The management communication bus system of claim 13, wherein said at least one slave device comprises:

an interface for detecting said cycle definition signal and for asserting data during a read cycle and for retrieving data during a write cycle; and

memory coupled to said interface for storing said data.

15. The management communication bus system of claim 10, further comprising:

a plurality of bus master devices coupled to said bus, each having an identification number with a predetermined priority; and

wherein each of said plurality of bus master devices includes an interface for asserting a binary equivalent of an identification number on said plurality of bus data signals to arbitrate for said bus, wherein a bus master device asserting a highest priority identification number gains control of said bus.

16. The management communication bus system of claim 15, wherein said first bus state is divided into multiple phases, wherein during each of said multiple phases, each bus master device having a corresponding logic bit being equal to a predetermined priority logic level asserts said corresponding logic bit on a corresponding one of said plurality of bus data signals and then compares its corresponding logic bit with said corresponding one of said plurality of bus data signals, and wherein during a final phase, a bus master device having an identification code matching corresponding ones of said plurality of bus data signals gains control of said bus.

17. The management communication bus system of claim 15, wherein said first bus state is divided into multiple phases corresponding to the number of bits of said binary equivalent of said identification number, wherein during each of said multiple phases, each bus master device having a leading identification bit equal to a predetermined priority logic level asserts said leading identification bit and all consecutive identification bits equal to said predetermined priority logic level on corresponding ones of said plurality of bus data signals, and in each subsequent phase, each bus master drives additional identification bits if its more significant identification bits are equal to an opposite logic state as said predetermined priority logic level and match corresponding ones of said plurality of bus data signals.

18. The management communication bus system of claim 10, further comprising:

a plurality of slave devices each associated with one of a plurality of unique identification number; and

wherein said at least one bus master device includes an interface for asserting one of said plurality of unique identification numbers on said plurality of bus data signals to access a corresponding one of said plurality of slave devices.

19. The management communication bus system of claim 18, wherein said bus master interface asserts a global identification number on said plurality of bus data signals to access all of said plurality of slave devices.

20. The management communication bus system of claim 10, wherein said at least one slave device includes an interface for asserting a busy signal on one of said plurality of bus data signals during said second bus state to delay said third bus state.

21. A network system, comprising:

a chassis including a plurality of slots;

a plurality of slot connectors mounted to said chassis, each one of said plurality of slot connectors aligned with a corresponding one of said plurality of slots;

a management communication bus coupled to each of said plurality of slot connectors, said bus comprising;

a number of encoded bus state signals, where said number is greater than one, that collectively define more than said number of bus states including an identification state for arbitrating for control of said bus and for asserting a slave identification number, an address state for asserting an address and a data state for asserting data corresponding to said address; and

a plurality of bus data signals for transferring information data depending upon said bus states, said information data including bus request and slave identification information during said identification state, said address during said address state and said data during said data state; and

each bus data signal within said plurality of bus data signals has a definition, at least one of said definitions is operable to be redefined during a change of at least one of said number of bus states; and

at least one module for plugging into any one of said plurality of slots of said chassis including a module connector for coupling with a corresponding one of said plurality of slot connectors for interfacing said at least one module to said bus.

22. The network system of claim 21, wherein said at least one module includes a bus master device for asserting said number of encoded bus state signals to transition between said more than said number of bus states of said bus.

23. The network system of claim 22, wherein said bus master device includes an interface to assert said number of encoded bus state signals and said plurality of bus data signals to initiate said identification state and gain control of said bus, to assert said slave identification number, to advance to said address state and to assert an address, and to advance to said data state to perform a data cycle.

24. The network system of claim 21, wherein said at least one module includes a slave device for monitoring said plurality of bus data signals, for retrieving an address and for participating in a data cycle during said data state.

25. The network system of claim 24, wherein said slave device includes:

an interface for detecting a cycle definition signal and for asserting data during a read cycle and for retrieving data for a write cycle; and

memory coupled to said interface for storing said data.

26. The network system of claim 21, wherein said at least one module comprises:

a bus master device for asserting said number of encoded bus state signals to transition between said more than said number of bus states of said bus; and

a slave device for monitoring said plurality of bus data signals, for retrieving an address and for participating in a data cycle during said data state.

27. The network system of claim 21, wherein said at least one module comprises:

a first module including a bus master device for asserting said number of encoded bus state signals to transition between said more than said number of bus states of said bus; and

a second module including a slave device for monitoring said plurality of bus data signals, for retrieving an address and for participating in a data cycle during said data state.

28. The network system of claim 27, wherein said second module further comprises:

a network device, including;

a media interface device; and

port control logic coupled to said media interface device and said slave device,

said port control logic including a plurality of configuration and status registers.

29. The network system of claim 28, wherein said slave device further comprises:

a processor coupled to said port control logic; and

a slave interface coupled to said processor and said bus.