Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirements

• US 6,199,153 B1
• Filed: 06/18/1998
• Issued: 03/06/2001
• Est. Priority Date: 06/18/1998
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Razdan, Rahul, Katzman, Solomon J., Kessler, Richard E., Keller, James B.
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/099,383
• Time in Patent Office: 992 Days
• Field of Search: 710/66, 710/74, 710/127, 711/212, 711/201, 711/210
• US Class Current: 711/212
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

A computing apparatus has a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size. An address bus of the computing apparatus is configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size. The address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N.

Claims

1. A computing apparatus, comprising:

a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size;

an address bus configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size;

wherein the address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N;

an encoder configured to map the address bits into an encoded packet forming an array having N rows and C columns, each row and column defining a cell of the packet, and each address bit of the address bits being allocated to at least one of the cells;

said encoder also configured to arrange the address bits of the address into an encoded packet so that, in short-bus mode, the address bits defining the second memory size are transmitted over the M communications lines of the address bus; and

a controller for generating one or more bits indicating a probe miss;

wherein;

one or more of the cells of the encoded packet further includes at least one of the probe miss bits.

3. The computing apparatus of claim 1, further comprising:

said encoder configured to arrange the address bits of the address into an encoded packet so that, in short-bus mode, the address bits defining the second memory size are transmitted over the M communications lines of the address bus.

4. The computing apparatus of claim 1, further comprising:

an address generator generating the address.

5. The computing apparatus of claim 1, wherein the first memory size is a maximum memory size and the second memory size is a scaled-down memory size.

6. The computing apparatus of claim 1, further comprising:

N pins, each of the pins respectively attached to a corresponding one of the N communication lines.

7. The computing apparatus of claim 1, wherein:

one or more of the cells of the packet includes bits defining command information.

8. The computing apparatus of claim 1, wherein:

one or more of the cells of the packet includes bits defining control information.

10. The computing apparatus of claim 1, further comprising:

a time multiplexer configured to transmit the cells of the packet over the address bus in C time cycles, one of the columns of cells being transmitted during one of the C time cycles, the cells in the N rows of the one column being transmitted over the N communication lines in the one time cycle.

11. The computing apparatus of claim 1, wherein:

the mode selector is further configured to select a third memory size which is less than the first memory size;

the address bus is further configured to transmit an address consisting of a subset of the address bits defining the third memory size; and

wherein P of the N communication lines are each further configured to transmit one of a third number of bits of the address bits defining the third memory size in the short-bus mode, where P is less than N.

14. The computing apparatus of claim 1, wherein:

while in the short-bus mode, the address is generated to a memory greater than the second memory size, this memory being denoted as non-existent memory;

a non-existent memory detection unit for detecting the address to non-existent memory; and

a handling unit for canceling the address to non-existent memory.

2. A processor that can be connected to a memory controller which can be connected to a memory, said memory can be any of a plurality of sizes, comprising:

a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size;

an address bus configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size;

wherein the address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N;

an encoder configured to map the address bits into an encoded packet forming an array having N rows and C columns, each row and column defining a cell of the packet, and each address bit of the address bits being allocated to at least one of the cells wherein at least one of the cells of the packet contains a bit indicating a probe miss.

12. The computing apparatus of claim 2, wherein the encoded packet is divided into a plurality of parts, each part containing a portion of the address bits arranged so that the address defining the second memory size is transmitted over the N communication lines.

13. The computing apparatus of claim 12, further comprising:

a time multiplexer configured to transmit the encoded packet defining the second memory size over the M communications lines of the address bus by transmitting one of the parts per a time cycle.

9. A computing apparatus, comprising:

a mode selector configured to select one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is smaller than the first memory size;

an address bus configured to transmit an address consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size;

wherein the address bus has N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N;

an encoder configured to map the address bits into an encoded packet forming an array having N rows and C columns, each row and column defining a cell of the packet, and each address bit of the address bits being allocated to at least one of the cells;

said encoder also configured to arrange the address bits of the address into an encoded packet so that, in short-bus mode, the address bits defining the second memory size are transmitted over the M communications lines of the address bus; and

wherein at least one of the cells of the packet contains a bit indicating a probe miss.

15. A computing apparatus configured to address multiple sized memory spaces using a minimum number of pins, comprising:

an address unit configured to generate an address consisting of address bits, the address bits defining a maximum memory and a subset of the address bits defining a small memory which is smaller than the maximum memory;

a mode selector for selecting a long-bus mode corresponding to the maximum memory or a short-bus mode corresponding to the small memory;

an address bus having N communication lines;

an encoder unit for mapping the address bits into an encoded packet having N rows and C columns, each row and column defining a cell of the packet, and each address bit of the address being placed in at least one of the cells so that the address bits defining the small memory are communicable over M of the N communication lines and the address bits defining the maximum memory are communicable over the N communication lines; and

a time multiplexer for transmitting the cells of the packet over the address bus to an external system in C time cycles, one column of the packet transmitted in each of one of the C time cycles, the cells in the N rows of each column of the packet being transmitted in parallel over the N communication lines in one of the C time cycles wherein at least one of the cells of the packet contains a bit indicating a probe miss.

16. A method of accessing memory, comprising:

selecting one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size;

transmitting an address over an address bus consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size, the address bus having N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N; and

arranging the address bits of the address into an encoded packet forming an array having N rows and C columns, each row and column defining a cell of the packet, and each address bit of the address bits being allocated to at least one of the cells, said cells also including command and control information wherein at least one of the cells of the packet contains a bit indicating a probe miss.

17. The method of claim 16, further comprising:

arranging the address bits of the address into an encoded packet so that, in the short-bus mode, the address bits defining the second memory size are transmitted over the M communications lines of the address bus.

19. The method of claim 16, further comprising:

generating, while in the short-bus mode, an address to a memory greater than the second memory size, this memory being denoted as non-existent memory; and

further comprising substeps of;

detecting the address to the non-existent memory; and

canceling the detected address to the non-existent memory.

20. The method of claim 16, wherein the arranging step further includes:

partitioning the address bits to form a predetermined group of lower-order address bits and a predetermined group of higher-order address bits, wherein the address bits consisting of the concatenation of the lower-order address bits and the higher order address bits define a first address space and the lower-order address bits define a second address space;

arranging an encoded packet into C columns, each column consisting of N rows, each column and row defining a cell; and

allocating a portion of the bits of the address to cells in each one of the plurality of columns, including mapping the higher-order address bits to the cells of the columns so that rows 1 to M contain the lower-order address bits forming the second address space wherein M is less than N.

18. A method of accessing memory, comprising:

selecting one of a long-bus mode corresponding to a first memory size and a short-bus mode corresponding to a second memory size which is less than the first memory size;

transmitting an address over an address bus consisting of address bits defining the first memory size and a subset of the address bits defining the second memory size, the address bus having N communication lines each configured to transmit one of a first number of bits of the address bits defining the first memory size in the long-bus mode and M of the N communication lines each configured to transmit one of a second number of bits of the address bits defining the second memory size in the short-bus mode, where M is less than N; and

arranging the address bits of the address into an encoded packet forming an array having N rows and C columns, each row and column defining a cell of the packet, and each address bit of the address bits being allocated to at least one of the cells;

wherein at least one of the cells of the packet contains a bit indicating a probe miss.

21. A multiprocessor system, comprising:

a plurality of processor chips;

a main memory;

a control chip connecting the plurality of processor chips and the main memory; and

wherein each processor chip comprises;

a mode selector configured to select either the main memory having a first memory size or the main memory having a second memory size which is less than the first memory size;

N pins configured to transmit an address to the control chip corresponding to the first memory size,

M pins formed as a subset of the N pins configured to transmit an address to the control chip corresponding to the second memory size, where M is less than N; and

an encoder configured to transform the address into an encoded packet so that the address corresponding to the first memory size transmits over the N pins to the control chip and the address corresponding to the second memory size transmits over the M pins to the control chip, where M is less than N wherein at least one of the cells of the packet contains a bit indicating a probe miss.