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Probeless testing of pad buffers on wafer

  • US 6,199,182 B1
  • Filed: 03/27/1998
  • Issued: 03/06/2001
  • Est. Priority Date: 03/27/1997
  • Status: Expired due to Term
First Claim
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1. A semiconductor body having at least one integrated circuit formed at a surface thereof, the at least one integrated circuit comprising:

  • core functional logic;

    a terminal buffer coupled in a signal path between the core functional logic and a terminal pad, for forwarding a signal along the signal path;

    a load test switch for selectively connecting a load terminal to the signal path between the terminal buffer and the terminal pad and free of the terminal pad;

    a first test switch for selectively connecting an input of the terminal buffer to a first test terminal;

    a second test switch for selectively connecting an output of the terminal buffer to a second test terminal; and

    control circuitry for controlling the operation of the load test switch and the first and second test switches so as to be open in normal operation, and so as to be selectively closed in a test mode.

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