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Parallel signature compression circuit and method for designing the same

  • US 6,199,184 B1
  • Filed: 09/08/1998
  • Issued: 03/06/2001
  • Est. Priority Date: 09/08/1997
  • Status: Expired due to Term
First Claim
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1. A compression circuit for compressing response data from an electronic circuit under test, said compression circuit comprising:

  • a first multiple input signature register (MISR) that compresses the response data to generate a first signature;

    a second MISR coupled to said first MISR that compresses the first signature to generate a second signature and a third MISR coupled to said second MISR that compresses the second signature to generate a third signature.

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