Method to form a smooth gate polysilicon sidewall in the fabrication of integrated circuits

• US 6,200,887 B1
• Filed: 01/24/2000
• Issued: 03/13/2001
• Est. Priority Date: 01/24/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Kantimahanti, Arjun, Balasubramaniam, Palanivel, Balasubramanian, Narayanan, Pradeep, Yelehanka Ramachandramurthy
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/490,133
• Time in Patent Office: 414 Days
• Field of Search: 438/197, 438/299, 438/301, 438/516, 438/515, 438/527, 438/528, 438/529, 438/532, 438/585
• US Class Current: 438/585
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/31662 of silicon in uncombined form

Abstract

A method for forming gate structures with smooth sidewalls by amorphizing the polysilicon along the gate boundaries is described. This method results in minimal gate depletion effects and improved critical dimension control in the gates of smaller devices. The method involves providing a gate silicon oxide layer on the surface of the semiconductor substrate. A gate electrode layer, such as polysilicon is deposited over the gate silicon oxide followed by a masking oxide layer deposited over the gate electrode layer. The masking oxide layer is patterned for the formation of the gate electrode. An ion implantation of silicon or germanium amorphizes the area of the polysilicon not protected by the masking oxide mask and also amorphizes the area along the boundaries of the polysilicon gate. Thereafter, the amorphized silicon is then removed by an anisotropic etch leaving a narrow area of amorphized silicon on the gate electrode sidewalls under the edges of the masking oxide mask completing the gate structure having smooth sidewalls.

Claims

1. A method of forming a smooth edged polysilicon gate in an integrated circuit device comprising:

providing a gate oxide layer over the surface of a semiconductor substrate;

depositing a polysilicon layer overlying said gate oxide layer;

depositing a masking layer over said polysilicon layer;

patterning said masking layer to leave a mask overlying a region where said gate is formed;

ion implanting said polysilicon layer in portions not covered by said mask thereby amorphizing said polysilicon layer not covered by said mask and amorphizing a portion of said polysilicon layer covered by said mask by lateral diffusion of said ions; and

etching away said polysilicon layer not covered by said mask to form said polysilicon gate having a smooth region of said amorphized polysilicon layer along edges of said polysilicon gate to complete formation of said smooth edged polysilicon gate completing fabrication of said integrated circuit device.

2. The method according to claim 1 wherein said polysilicon layer is deposited to a thickness of between about 800 to 5000 Angstroms.

3. The method according to claim 2 wherein said polysilicon layer comprises polysilicon germanium.

4. The method according to claim 1 wherein said ions implanted into said polysilicon layer are silicon with a dosage of between about 8E14 to 5E15 atoms/cm² and energy varied between about 30 to 120 keV wherein said energy level is adjusted so that the projected depth covers the entire thickness of said polysilicon layer.

5. The method according to claim 1 wherein said ions implanted into said polysilicon layer are germanium with a dosage of between about 5E14 to 5E15 atoms/cm² and energy varied between about 50 to 270 keV wherein said energy level is adjusted so that the projected depth covers the entire thickness of said polysilicon layer.

6. The method according to claim 1 wherein said ions implanted into said polysilicon layer comprise one of the group containing silicon, germanium, phosphorous, boron and BF₂ with a dosage of between about 5E14 to 5E15 atoms/cm² and energy varied between about 30 to 270 keV wherein said energy level is adjusted so that the projected depth covers the entire thickness of said polysilicon layer.

7. The method according to claim 1 wherein said step of etching of said polysilicon layer is performed with an endpoint detection followed by an overetch of between about 10 to 150%.

8. The method according to claim 1 wherein said gate oxide layer is composed of silicon oxide deposited by dry or partial wet oxidation with a NH₄/N₂O anneal at a temperature of between about 700 to 900°

C. to a thickness of between about 10 to 150 Angstroms.

9. The method according to claim 1 wherein said gate oxide layer is composed of silicon oxide deposited or grown by RTO at a temperature of between about 400 to 1000°

C. to a thickness of between about 10 to 150 Angstroms.

10. A method of forming a smooth edged polysilicon gate in an integrated circuit device comprising:

providing a gate oxide layer over the surface of a semiconductor substrate;

depositing a polysilicon layer overlying said gate oxide layer;

depositing a masking layer over said polysilicon layer;

patterning said masking layer to leave a mask overlying a region where said gate is formed;

ion implanting said polysilicon layer in at least two steps with increasing energy levels in portions not covered by said mask thereby amorphizing said polysilicon layer not covered by said mask and amorphizing a portion of said polysilicon layer covered by said mask by lateral diffusion of said ions; and

etching away said polysilicon layer not covered by said mask to form said polysilicon gate having a smooth region of said amorphized polysilicon layer along the edges of said polysilicon gate to complete formation of said smooth edged polysilicon gate in the fabrication of said integrated circuit device.

11. The method according to claim 10 wherein said polysilicon layer is deposited to a thickness of between about 800 to 5000 Angstroms.

12. The method according to claim 11 wherein said polysilicon layer comprises polysilicon germanium.

13. The method according to claim 10 wherein said ions implanted into said polysilicon layer are silicon with a dosage of between about 8E14 to 5E15 atoms/cm² and energy varied between about 30 to 120 keV wherein said energy level is adjusted so that the projected depth covers the entire thickness of the polysilicon layer.

14. The method according to claim 10 wherein said ions implanted into said polysilicon layer are germanium with a dosage of between about 5E14 to 5E15 atoms/cm² and energy varied between about 50 to 270 keV wherein said energy level is adjusted so that the projected depth covers the entire thickness of the polysilicon layer.

15. The method according to claim 10 wherein said ions implanted into said polysilicon layer comprise one of the group containing silicon, germanium, phosphorous, boron and BF₂ with a dosage of between about 5E14 to 5E15 atoms/cm² and energy varied between about 30 to 270 keV wherein said energy level is adjusted so that the projected depth covers the entire thickness of the polysilicon layer.

16. The method according to claim 10 wherein said step of etching of said polysilicon layer is performed with an endpoint detection followed by an overetch of between about 10 to 150%.

17. A method of forming a smooth edged polysilicon gate in an integrated circuit device comprising:

providing a gate oxide layer over the surface of a semiconductor substrate;

depositing a polysilicon layer overlying said gate oxide layer;

depositing a masking layer over said polysilicon layer;

patterning said masking layer to leave a mask overlying a region where said gate is formed;

ion implanting said polysilicon layer in portions not covered by said mask wherein said ions are implanted at a first energy level of between about 30 to 50 keV, a second energy level of between about 60 to 80 keV, and a third energy level of between about 90 to 120 keV, thereby amorphizing said polysilicon layer not covered by said mask and amorphizing a portion of said polysilicon layer covered by said mask by lateral diffusion of said ions; and

etching away said polysilicon layer not covered by said mask to form said polysilicon gate having a smooth region of said amorphized polysilicon layer along the edges of said polysilicon gate to complete formation of said smooth edged polysilicon gate in the fabrication of said integrated circuit device.

18. The method according to claim 17 wherein said polysilicon layer is deposited to a thickness of between about 800 to 5000 Angstroms.

19. The method according to claim 18 wherein said polysilicon layer comprises polysilicon germanium.

20. The method according to claim 17 wherein said ions implanted into said polysilicon layer are silicon at a dosage of between about 8E14 to 5E15 atoms/cm².

21. The method according to claim 17 wherein said ions implanted into said polysilicon layer are germanium at a dosage of between about 5E14 to 5E15 atoms/cm².

22. The method according to claim 17 wherein said ions implanted into said polysilicon layer comprise one of the group containing silicon, germanium, phosphorous, boron and BF₂.

23. The method according to claim 17 wherein said step of etching of said polysilicon layer is performed with an endpoint detection followed by an overetch of between about 10 to 150%.