Group III nitride photonic devices on silicon carbide substrates with conductive buffer interlay structure

• US 6,201,262 B1
• Filed: 10/07/1997
• Issued: 03/13/2001
• Est. Priority Date: 10/07/1997
• Status: Expired due to Term

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Edmond, John Adam, Kong, Hua-Shuang, Doverspike, Kathleen Marie, Leonard, Michelle Turner
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Lee, Calvin
• Application Number:
  US08/944,547
• Time in Patent Office: 1,253 Days
• Field of Search: 257/103, 257/77, 257/78, 257/79, 257/96, 257/97, 148/33
• US Class Current: 257/77
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02642 Mask materials other than SiO2 or SiN
• CPC Class Codes: H01L 33/007 comprising nitride compounds

Abstract

An optoelectronic device with a Group III Nitride active layer is disclosed that comprises a silicon carbide substrate; an optoelectronic diode with a Group III nitride active layer; a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between the silicon carbide substrate and the optoelectronic diode; and a stress-absorbing structure comprising a plurality of predetermined stress-relieving areas within the crystal structure of the buffer structure, so that stress-induced cracking that occurs in the buffer structure occurs at predetermined areas rather than elsewhere in the buffer structure.

Claims

1. An optoelectronic device with a Group III Nitride active layer, said device comprising:

a conductive silicon carbide substrate;

an ohmic contact to said substrate;

an optoelectronic diode with a Group III nitride active layer;

a buffer structure selected from the group consisting of gallium nitride and indium gallium nitride between said silicon carbide substrate and said optoelectronic diode; and

a stress-absorbing structure comprising a predetermined grid pattern of grooves in the surface of said silicon carbide substrate and a corresponding grid pattern of stress-absorbing areas propagated into said buffer from said grooves in said substrate, so that stress-induced cracking that occurs in said buffer structure occurs at said predetermined areas rather than elsewhere in said buffer structure.

2. An optoelectronic device according to claim 1 wherein said buffer structure is conductive.

3. An optoelectronic device according to claim 1 comprising a light emitting diode.

4. A pixel that incorporates a light emitting diode according to claim 3.

5. A display that incorporates a plurality of pixels according to claim 4.

6. An optoelectronic device according to claim 1 comprising a laser diode.

7. An optoelectronic device according to claim 1 wherein said grid defines squares of about 250 microns per side.

8. An optoelectronic device according to claim 1 wherein said grid defines rectangles of about 250 by 500 microns.

9. An optoelectronic device according to claim 1 wherein said diode is selected from the group consisting of p-n homojunctions, p-n single and double heterojunctions, and p-n quantum junction well structures.

10. An optoelectronic device according to claim 1 wherein said silicon carbide substrate has a polytype selected from the group consisting of the 3C, 4H, 6H, and 15R polytypes.

11. An optoelectronic device according to claim 1 wherein said Group III nitride active layer comprises gallium nitride.

12. An optoelectronic device according to claim 1 wherein said Group III nitride comprises indium gallium nitride.

13. A wafer precursor for Group III nitride devices, said precursor wafer comprising:

a silicon carbide substrate wafer;

a buffer layer on said substrate and selected from the group consisting of gallium nitride and indium gallium nitride; and

a stress-absorbing structure comprising a predetermined grid pattern of grooves in the surface of said silicon carbide substrate wafer and a corresponding grid pattern of stress absorbing areas propagated into said buffer from said grooves in said substrate, so that stress induced cracking that occurs in said buffer layer occurs at said predetermined areas rather than elsewhere in said buffer structure.

14. A wafer precursor according to claim 13 wherein said grid defines squares of about 250 microns per side.

15. A wafer precursor according to claim 13 wherein said grid defines rectangles of about 250×

500 microns.

16. A wafer precursor according to claim 13 wherein said silicon carbide substrate has a polytype selected from the group consisting of the 3C, 4H, 6H, and 15R polytypes.