Compact low power complement FETs

• US 6,201,267 B1
• Filed: 03/01/1999
• Issued: 03/13/2001
• Est. Priority Date: 03/01/1999
• Status: Expired due to Term

• Current Assignee: Rensselaer Polytechnic Institute
• Original Assignee: Rensselaer Polytechnic Institute
• Inventors: Gupta, Rajesh N., Shur, Michael
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US09/260,320
• Time in Patent Office: 743 Days
• Field of Search: 257/369, 257/371, 257/368, 257/206, 438/199
• US Class Current: 257/206
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A complementary Field Effect Transistor includes a first transistor and a second transistor stacked on the first transistor. The angle between the source/drain pair for the first transistor and the source/drain pair for the second transistor is nonzero and other than 180 degrees (e.g., 90 degrees). In one embodiment, each transistor has its own gate, and the active regions for the transistors are separated and situated between the gates. In another embodiment, the active regions for the transistors share a single channel region. In still another embodiment, the transistors share a single gate. In yet another embodiment, the transistors share both a channel region and a gate.

Claims

1. A semiconductor device, comprising:

a first Field Effect Transistor (FET) having a first gate, a first channel region and a first source/drain pair;

a second FET complementary to and vertically adjacent the first FET, and having a second gate separate from the first gate, a second channel region and a second source/drain pair;

wherein an angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees; and

wherein the first channel region and the second channel region are situated between the first gate and the second gate.

2. The semiconductor device of claim 1, wherein the first channel region and the first source/drain pair are separated from the second channel region and the second source/drain pair by an insulating barrier layer.

4. The semiconductor device of claim 1, further comprising an insulating substrate on which one of the first gate and the second gate is deposited, wherein the first channel region and the second channel region comprise intrinsic polycrystalline silicon (polysilicon), wherein one of the first source/drain pair and the second source/drain pair comprises P-type polysilicon, and wherein the other of the first source/drain pair and the second source/drain pair comprises N-type polysilicon.

5. The semiconductor device of claim 1, further comprising a semi-insulating substrate on which one of the first gate and the second gate is deposited, wherein the first channel region and the second channel region comprise a narrow bandgap semiconductor material, wherein one of the first source/drain pair and the second source/drain pair comprises a P-type narrow bandgap semiconductor material, and wherein the other of the first source/drain pair and the second source/drain pair comprises an N-type narrow bandgap semiconductor material.

3. A semiconductor device, comprising:

a first Field Effect Transistor (FET) having a first gate, a first channel region and a first source/drain pair;

a second FET complementary to and vertically adjacent the first FET, and having a second gate separate from the first gate, a second channel region and a second source/drain pair;

wherein an angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees;

wherein the first channel region and the second channel region are situated between the first gate and the second gate; and

wherein the first channel region and the second channel region comprise a common channel region.

6. A semiconductor device, comprising:

a first Field Effect Transistor (FET) having a first channel region and a first source/drain pair;

a second FET complementary to and vertically adjacent the first FET, and having a second source/drain pair and a second channel region;

at least one gate common to the first FET and the second FET; and

wherein an angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees.

7. The semiconductor device of claim 6, wherein the first channel region and the first source/drain pair are separated from the second channel region and the second source/drain pair by an insulating barrier layer.

8. The semiconductor device of claim 6, wherein the first channel region and the second channel region comprise a common channel region.

9. The semiconductor device of claim 6, wherein the at least one gate comprises a plurality of gates.

10. The semiconductor device of claim 6, further comprising a semi-insulating substrate on which one of the first channel region and the second channel region is deposited, wherein the first channel region and the second channel region comprise intrinsic polycrystalline silicon (polysilicon), wherein one of the first source/drain pair and the second source/drain pair comprises P-type polysilicon, and wherein the other of the first source/drain pair and the second source/drain pair comprises N-type polysilicon.

11. The semiconductor device of claim 6, further comprising a semi-insulating substrate on which one of the first channel region and the second channel region is deposited, wherein the first channel region and the second channel region comprise a narrow bandgap semiconductor material, wherein one of the first source/drain pair and the second source/drain pair comprises a P-type narrow bandgap semiconductor material, and wherein the other of the first source/drain pair and the second source/drain pair comprises an N-type narrow bandgap semiconductor material.

12. A semiconductor device, comprising:

an insulating substrate;

a first Field Effect Transistor (FET) on the insulating substrate having a first source/drain pair comprising one of P-type polysilicon and N-type polysilicon;

a second FET on the insulating substrate having a second source/drain pair comprising the other of P-type polysilicon and N-type polysilicon;

a gate common to the first FET and the second FET;

a channel region common to the first FET and the second FET comprising intrinsic polysilicon;

wherein an angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees.

13. The semiconductor device of claim 12, further comprising an insulating barrier layer between the gate and the channel region.

14. A semiconductor device, comprising:

a semi-insulating substrate;

a narrow bandgap semiconductor layer on the semi-insulating substrate;

a wide bandgap semiconductor layer on the narrow bandgap semiconductor layer;

a first Field Effect Transistor (FET) on the wide bandgap semiconductor layer having a first source/drain pair comprising one of a P-type narrow bandgap semiconductor material and an N-type narrow bandgap semiconductor material;

a second FET on the wide bandgap semiconductor layer having a second source/drain pair comprising the other of P-type narrow bandgap semiconductor material and N-type narrow bandgap semiconductor material;

a gate common to the first FET and the second FET;

a channel region common to the first FET and the second FET comprising unintentionally doped InGaAs;

wherein an angle between the first source/drain pair and the second source/drain pair is nonzero and other than 180 degrees.

15. The semiconductor device of claim 14, further comprising an insulating barrier layer between the gate and the channel region.