High speed CMOS photodetectors with wide range operating region and fixed pattern noise reduction

• US 6,201,270 B1
• Filed: 08/11/1999
• Issued: 03/13/2001
• Est. Priority Date: 04/07/1997
• Status: Expired due to Fees

• Current Assignee: Pao-Jung Chen
• Original Assignee: Pao-Jung Chen
• Inventors: Chen, Pao-Jung
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US09/372,687
• Time in Patent Office: 580 Days
• Field of Search: 257/292, 257/461, 250/214.1, 327/514, 327/515
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/57 Control of the dynamic range
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A CMOS charge-integration mode photo-detector built on an n-type substrate is disclosed in this invention. This photo-detector includes a p+n photodiode with the n-type substrate constituting an n-region and a p+ diffusion region disposed near a top surface of the n-type substrate, the p+ diffusion region constituting a charge integration node. The photodetector further includes a gate-biased charge storable n-type MOS transistor functioning as a photo-conversion voltage amplifier supported on the substrate formed with a threshold voltage of Vt0 having a gate terminal connected to the charge-integration node. The photodetector further includes a MOS transistor supported on the substrate functioning as a constant current-source load transistor having a drain terminal connected to a source terminal of the gate-biased charge storable n-type MOS transistor and a gate terminal connected to a bias reference voltage. The photodetector further includes a pre-charge switch transistor supported on the substrate having a source terminal connected to charge-integration node and a drain terminal connected to a bias voltage source. (The photodetector further includes a MOS transistor supported on the substrate functioning as a readout switch transistor having a source terminal connected to a drain terminal of the gate-biased charge storable n-type MOS transistor). In an alternate preferred embodiment, the photodetector is formed in a p-type substrate.

Claims

1. A CMOS photodetector supported on a substrate comprising:

a p-n junction diode having a charge-integration node;

a gate-biased charge storable MOS transistor having a gate terminal connected to the charge-integration node of said p-n junction diode;

a readout switch MOS transistor connected to a source terminal of said charge storable MOS transistor;

a bias charge pre-charge switch MOS transistor connected to said charge-integration node responsive to a control signal for providing a source of voltage reference as a pre-charge bias voltage to said gate terminal of said gate-biased charge storable MOS transistor;

a second gate-biased charge storable MOS transistor;

a second readout switch MOS transistor having a drain terminal connected to a source terminal of said second charge storable MOS transistor and a gate terminal connected to a gate terminal of said readout switch MOS transistor; and

a second bias charge pre-charge switch MOS transistor having a gate terminal connected to a power supply bus Vdd, a drain terminal connected to said voltage reference and a source terminal connected to a gate terminal of said second gate-biased charge storable MOS transistor.

2. The photodetector of claim 1 wherein:

said substrate is a p-type substrate, said p-n junction diode is an n+p junction diode and said gate-biased charge storable MOS transistor is an NMOS transistor.

3. A linear array of photo-detectors of claim 1 further comprising:

a digital scanning shift register having a plurality of bits each being connected to a gate terminal of each of said readout switch transistor for sequentially reading out a video signal detected by each of said photodetectors, and connected to each of said bias charge pre-charge switch transistor for resetting to said voltage reference;

a resettable capacitor and current-source load source follower readout circuit including a buffer amplifier connected to a common source terminal of said readout switch transistor for receiving an output signal sequentially from each of said photodetectors; and

a second resettable capacitor and current-source load source follower readout circuit including a buffer amplifier connected to a common source terminal of said second readout switch transistor for receiving an output signal sequentially from each of said photodetectors.

4. The photodetector of claim 1 wherein:

said substrate is a p-type substrate, said p-n junction diode is an n+p junction diode and said gate-biased charge storable MOS transistor is an NMOS transistor.

5. A linear array of photo-detectors of claim 1 further comprising:

a four-bus readout structure having the first bus connected to a common source terminal of said second readout switch transistor of each odd number photodetector of said photodetectors, having the second bus connected to a common source terminal of said readout switch transistor of each odd number photodetector of said photodetectors, the third bus connected to a common source terminal of said second readout switch transistor of each even number photodetector of said photodetectors and the fourth bus connected to a common source terminal of said readout switch transistor of each even number photodetector of said photodetectors.

6. A linear array of photo-detectors of claim 1 further comprising:

a digital scanning shift register having a plurality of bits each being connected to a gate terminal of each of said readout switch transistor of said photodetectors for sequentially reading out a video signal detected by each of said photodetectors, and connected to each of said bias charge pre-charge switch transistor for resetting to said voltage reference;

a first resettable capacitor and current-source load source follower readout circuit including a buffer amplifier connected to a common source terminal of said second readout switch transistor of said first readout bus for receiving an output signal sequentially from each of said odd-number photodetectors;

a second resettable capacitor and current-source load source follower readout circuit including a buffer amplifier connected to a common source terminal of said readout switch transistor of said second readout bus for receiving an output signal sequentially from each of said odd-number photodetectors;

a third resettable capacitor and current-source load source follower read-out circuit including a buffer amplifier connected to a common source terminal of said second readout switch transistor of said third readout bus for receiving an output signal sequentially from each of said even-number photodetectors; and

a fourth resettable capacitor and current-source load source follower readout circuit including a buffer amplifier connected to a common source terminal of said readout switch transistor of said fourth readout bus for receiving an output signal sequentially from each of said photodetectors.