Trench transistor with insulative spacers

• US 6,201,278 B1
• Filed: 02/24/1998
• Issued: 03/13/2001
• Est. Priority Date: 10/30/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Dawson, Robert, Michael, Mark W., Wristers, Derick J., Hause, Frederick N., Gardner, Mark I., Fulford, H. Jim Jr., Moore, Bradley T.
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/028,896
• Time in Patent Office: 1,113 Days
• Field of Search: 257/330, 257/327, 257/332, 257/334, 257/336, 257/344, 257/401, 257/408, 257/900, 438/282, 438/585, 438/586, 438/589, 438/305, 438/306, 438/560
• US Class Current: 257/330
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, depositing a blanket layer of insulative spacer material over the substrate and applying an anisotropic etch to form the insulative spacers on the sidewalls, growing the gate insulator on a central portion of the bottom surface between the insulative spacers, depositing a gate electrode material on the gate insulator and the insulative spacers, polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate, and applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, thereby forming a source and drain with channel junctions substantially aligned with the gate electrode. Advantageously, the channel length is significantly smaller than the trench length.

Claims

1. An IGFET, comprising:

a semiconductor substrate including a trench;

a gate insulator on a bottom surface of the trench;

a non-floating gate electrode on the gate insulator, wherein the gate electrode has a planar top surface and a majority of a thickness of the gate electrode is in the trench;

insulative spacers between the gate electrode and opposing sidewalls of the trench, wherein the insulative spacers have planar top surfaces that are coplanar with the planar top surface of the non-floating gate electrode;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the planar top surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the bottom surface.

2. The IGFET of claim 1, wherein the source and the drain are adjacent to the sidewalls and extend to a top surface of the substrate.

3. The IGFET of claim 2, wherein the source and the drain include lightly doped regions adjacent to the bottom surface and heavily doped regions adjacent to the sidewalls.

4. The IGFET of claim 1, wherein the bottom surface includes a central portion spaced from the sidewalls, the gate insulator is on the central portion, and the insulative spacers are outside the central portion.

5. The IGFET of claim 4, wherein the insulative spacers are on the sidewalls and the bottom surface outside the central portion.

6. The IGFET of claim 4, wherein the gate insulator is on all of the bottom surface, sidewall insulators are on the sidewalls, and the insulative spacers are on the sidewall insulators and on the gate insulator outside the central portion.

7. The IGFET of claim 4, wherein the central portion is substantially aligned with a channel between the source and the drain, and with a bottom surface of the gate electrode.

8. The IGFET of claim 1, wherein the gate electrode is substantially aligned with a planar top surface of the substrate, and substantially all of the gate electrode is within the trench.

9. An integrated circuit chip including the IGFET of claim 1.

10. An electronic system, including a microprocessor, a memory, and a system bus, wherein the electronic system further includes the IGFET of claim 1.

16. The IGFET of claim 1 wherein the gate electrode is substantially aligned with the top surface.

17. The IGFET of claim 1, wherein substantially all of the gate electrode is within the trench.

24. The IGFET of claim 1, wherein the insulative spacers are substantially aligned with the top surface.

26. The IGFET of claim 1, wherein essentially all of a thickness of the gate electrode and the insulative spacers is in the trench.

29. The IGFET of claim 1, wherein substantially all of the gate electrode is within the trench and no portion of the gate electrode overlaps the top surface.

11. An IGFET, comprising:

a semiconductor substrate doped a first conductivity type including a trench extending beneath a top surface, wherein the trench includes first and second opposing sidewalls and a bottom surface, and the bottom surface includes a central portion between and spaced from the sidewalls;

first and second insulative spacers in the trench outside the central portion, wherein the insulative spacers have planar top surfaces;

a gate insulator in the trench on the central portion;

a non-floating gate electrode in the trench and on the gate insulator and on sides of the insulative spacers opposite the sidewalls, wherein the gate electrode is spaced from and electrically isolated from the substrate, the gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers, and a majority of a thickness of the gate electrode is in the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the planar top surface of the non-floating gate electrode;

a source doped a second conductivity type in the substrate, wherein the source extends between the top and bottom surfaces, is adjacent to the first sidewall, and is adjacent to the bottom surface;

a drain doped a second conductivity type in the substrate, wherein the drain extends between the top and bottom surfaces, is adjacent to the second sidewall, and is adjacent to the bottom surface; and

a channel doped the first conductivity type in the substrate, wherein the channel extends between the source and the drain and is adjacent to the central portion.

12. The IGFET of claim 11, wherein the first insulative spacer contacts the first sidewall and the bottom surface between the first sidewall and the central portion, and the second insulative spacer contacts the second sidewall and the bottom surface between the second sidewall and the central portion.

13. The IGFET of claim 11, wherein the gate insulator contacts all of the bottom surface, and the first and second insulative spacers contact the gate insulator outside the central portion.

14. The IGFET of claim 13, wherein the first and second insulative spacers contact sidewall insulators adjacent to the first and second sidewalls, respectively.

15. The IGFET of claim 11, wherein the channel is substantially aligned with the central portion, and a bottom surface of the gate electrode is substantially aligned with the central portion.

18. The IGFET of claim 11, wherein the gate electrode is polysilicon, the gate insulator is silicon dioxide, and the insulative spacers are selected from the group consisting of silicon dioxide, silicon nitride and undoped polysilicon.

19. The IGFET of claim 11, wherein a length of the channel is less than half of a length between the sidewalls.

20. The IGFET of claim 11, wherein a length of the channel is less than 2000 angstroms.

21. The IGFET of claim 11, wherein the source and the drain contact the insulative spacers at the sidewalls and the bottom surface.

22. The IGFET of claim 11, wherein the source and drain include lightly doped source and drain regions adjacent to the bottom surface and displaced from the top surface, and the source and drain include heavily doped source and drain regions adjacent to the top surface.

23. The IGFET of claim 11, wherein the source and the drain form channel junctions substantially aligned with a bottom surface of the gate electrode.

25. The IGFET of claim 11, wherein the gate electrode and the insulative spacers have essentially identical thicknesses.

27. The IGFET of claim 25, wherein the source and the drain contact the insulative spacers at the sidewalls and the bottom surface.

28. The IGFET of claim 25, wherein a length of the channel is less than half of a length between the sidewalls.

30. The IGFET of claim 25, wherein the gate electrode, the gate insulator and the insulative spacers are the only items in the trench.

31. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces;

a gate insulator on a bottom surface of the trench;

a non-floating gate electrode on the gate insulator, wherein the gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers, and the insulative spacers are between the gate electrode and opposing sidewalls of the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the top and bottom surfaces.

32. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces;

a gate insulator on a bottom surface of the trench;

a non-floating gate electrode on the gate insulator, wherein the gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers, and the insulative spacers are between the gate electrode and opposing sidewalls of the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the bottom surface, wherein a length of a channel between the source and the drain is less than half of a length between the sidewalls.

33. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces and the insulative spacers are formed from a single layer of deposited and anisotropically etched insulative material and contact opposing sidewalls and a bottom surface of the trench;

a gate insulator on the bottom surface and between the insulative spacers, wherein the gate insulator is thermally grown;

a non-floating gate electrode on the gate insulator and the insulative spacers, wherein the gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers and a majority of a thickness of the gate electrode is in the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the bottom surface.

34. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces and the insulative spacers contact opposing sidewalls and a bottom surface of the trench;

a gate insulator on a bottom surface of the trench;

a non-floating gate electrode on the gate insulator and the insulative spacers, wherein the non-floating gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers and a majority of a thickness of the gate electrode is in the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the bottom surface.

35. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces;

a gate insulator on a bottom surface of the trench;

a non-floating gate electrode on the gate insulator and the insulative spacers, wherein the gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers, and the gate electrode, the insulative spacers and the gate insulator are the only items in the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the bottom surface.

36. An IGFET, consisting of:

a semiconductor substrate with a trench;

an insulative layer on and completely covering a bottom surface and opposing sidewalls of the trench;

insulative spacers in the trench and on the insulative layer, wherein the insulative spacers are displaced from the substrate, and a central portion of the insulative layer on the bottom surface and between the spacers forms a gate insulator;

a gate electrode on the gate insulator, wherein the insulative spacers are between the gate electrode and the sidewalls, and a majority of a thickness of the gate electrode is in the trench; and

a source and a drain in the substrate and adjacent to the bottom surface.

37. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers;

a gate insulator on a bottom surface of the trench;

a non-floating gate electrode on the gate insulator, wherein the gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers, the insulative spacers are between the gate electrode and opposing sidewalls of the trench, and a majority of a thickness of the gate electrode is in the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate, wherein the source and drain include lightly doped source and drain regions adjacent to the bottom surface and displaced from the top surface, and the source and drain include heavily doped source and drain regions adjacent to the top surface and displaced from the bottom surface.

38. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces and the insulative spacers contact opposing sidewalls and a bottom surface of the trench;

a gate insulator on the bottom surface and between the insulative spacers;

a non-floating gate electrode on the gate insulator and the insulative spacers, wherein the non-floating gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers, a majority of a thickness of the gate electrode is in the trench, and the gate electrode, the insulative spacers and the gate insulator are the only items in the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the bottom surface.

39. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces and the insulative spacers contact opposing sidewalls and a bottom surface of the trench;

a gate insulator on the bottom surface and between the insulative spacers;

a non-floating gate electrode on the gate insulator and the insulative spacers, wherein the non-floating gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers, essentially all of the gate electrode and the insulative spacers is in the trench, and the gate electrode, the insulative spacers and the gate insulator are the only items in the trench;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the bottom surface.

40. An IGFET, comprising:

a semiconductor substrate with a trench;

insulative spacers in the trench, wherein the insulative spacers have planar top surfaces;

a gate insulator on a bottom surface of the trench;

a non-floating gate electrode on the gate insulator and the insulative spacers, wherein the gate electrode has a planar top surface that is coplanar with the planar top surfaces of the insulative spacers;

insulative segments on the substrate, wherein the insulative segments are adjacent to the insulative spacers and the insulative segments have planar top surfaces that are coplanar with the planar top surfaces of the insulative spacers and with the top planar surface of the non-floating gate electrode; and

a source and a drain in the substrate and adjacent to the top and bottom surfaces.