CMOS voltage reference with a nulling amplifier

• US 6,201,379 B1
• Filed: 10/13/1999
• Issued: 03/13/2001
• Est. Priority Date: 10/13/1999
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: MacQuigg, David R., Mercer, Mark J.
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Vu, Bao Q.
• Application Number:
  US09/416,899
• Time in Patent Office: 517 Days
• Field of Search: 323/313, 323/314, 323/315, 323/316
• US Class Current: 323/313
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage

Abstract

A CMOS voltage reference comprises a band-gap core, a primary amplifier and a “nulling” amplifier. The voltage reference may also include slope, level and curvature trim circuits to provide a low-cost CMOS voltage reference that can be trimmed after final packaging. Due to the nulling of the errors from other sources by the nulling amplifier, the trim circuits are able to adjust the variations from the band-gap core. The nulling amplifier uses switching techniques to provide an accurate null, but is configured to avoid injecting switch transients into the voltage reference output.

Claims

1. A CMOS voltage reference comprising:

a band-gap core;

a primary amplifier; and

an offset nulling amplifier, where in the an input of the offset nulling amplifier is electrically connected to an output of the band-zap core, wherein the offset nulling amplifier receives an output of the band-gap core and integrates a signal from the output of the band-gap core and applies a correction signal to a primary loop of the primary amplifier to force a null at the band-gap core.

2. The CMOS voltage reference of claim 1, wherein the offset nulling amplifier is outside of a signal path of the primary amplifier.

3. The CMOS voltage reference of claim 2, wherein the nulling amplifier nulls offsets and noise associated with the primary amplifier.

4. The CMOS voltage reference of claim 3, wherein the nulling amplifier integrates an offset at the input of the primary amplifier, and applies a correction signal to adjust the offset to zero.

5. The CMOS voltage reference of claim 4, wherein the correction signal is used for only a relatively slow adjustment of the offset of the primary amplifier.

6. A CMOS voltage reference comprising:

a band-gap core;

a primary amplifier; and

an offset nulling amplifier, wherein the offset nulling amplifier is outside of a signal path of the primary amplifier, wherein the nulling amplifier nulls offsets and noise associated with the primary amplifier, wherein the nulling amplifier integrates an offset at the input of the primary amplifier, and applies a correction signal to adjust the offset to zero, wherein the correction signal is used for only a relatively slow adjustment of the offset of the primary amplifier, wherein the primary amplifier is optimized for a fast continuous response, and the nulling amplifier is optimized for low-offset.

7. The CMOS voltage reference of claim 6, further comprising an output FET connected to an output of the primary amplifier.

8. The CMOS voltage reference of claim 7, further comprising a slope trim circuit.

9. The CMOS voltage reference of claim 8, further comprising a level trim circuit.

10. The CMOS voltage reference of claim 9, further comprising a curvature trim circuit.

11. The CMOS voltage reference of claim 10, wherein the slope and level trim circuits sink and/or source current in order to adjust the slope and level, respectively.

12. The CMOS voltage reference of claim 11, wherein the curvature trim circuit comprises at least one resistor that is non-linear over temperature.

13. The CMOS voltage reference of claim 12, further comprising a level select for selecting a desired output voltage level.

14. The CMOS voltage reference of claim 13, wherein the slope, level, and curvature trims are adjusted via a non-volatile memory after the voltage reference is packaged.

15. A CMOS voltage reference comprising:

a band-gap core;

a primary amplifier connected to the band-gap core;

an offset nulling amplifier connected to the primary amplifier, wherein the an input of the offset nulling amplifier is electrically connected to an output of the band-gap core, wherein the offset nulling amplifier receives an output of the band-gap core and integrates a signal from the output of the band-gap core and applies a correction signal to a primary loop of the primary amplifier to force a null at the band-gap cores;

a slope trim circuit; and

a level trim circuit;

wherein the slope and level trim circuits sink and/or source current into the band-gap core to adjust the slope and level of an output voltage of the reference.

16. The CMOS voltage reference of claim 15, wherein the nulling amplifier is outside of a signal path of the primary amplifier and nulls offsets and noise associated with the primary amplifier.

17. A CMOS voltage reference comprising:

a band-gap core;

a primary amplifier connected to the band-gap core;

an offset nulling amplifier connected to the primary amplifier;

a slope trim circuit; and

a level trim circuit;

a curvature trim circuit, the curvature trim circuit comprising at least one resistor that is non-linear with temperature;

wherein the slope and level trim circuits sink and/or source current into the band-gap core to adjust the slope and level of an output voltage of the reference, wherein the nulling amplifier is outside of a signal path of the primary amplifier and nulls offsets and noise associate with the privy amplifier.

18. A CMOS voltage reference comprising:

a band-gap core;

a primary amplifier connected to the band-gap core;

an offset nulling amplifier connected across the primary amplifier, wherein the an input of the offset nulling amplifier is electrically connected to an output of the band-gap core, wherein the offset nulling amplifier receives an output of the band-gap core and integrates a signal from the output of the band-gap core and applies a correction signal to a primary loop of the primary amplifier to force a null at the band-gap core; and

a curvature trim circuit comprising at least one resistor that is non-linear with temperature.

19. The CMOS voltage reference of claim 18, wherein the nulling amplifier is outside of a signal path of the primary amplifier and nulls offsets and noise associated with the primary amplifier.

20. A CMOS voltage reference comprising:

a band-gap core comprising two transistors;

a primary amplifier comprising;

a first gain stage connected to the band-gap core;

a second gain stage connected to the first gain stage;

a third gain stage connected to the second gain stage and the band-gap core;

a current mirror connected to the first, second and third gain stages;

an overall feedback loop comprising the first gain stage, the second gain stage and the third gain stage; and

a secondary feedback loop comprising the current mirror, the second gain stage and the third gain stage;

an offset nulling amplifier connected across the primary amplifier;

a slope trim circuit having an output selectably connected to one transistor in the band-gap core;

a level trim circuit connected to the bases of the transistors in the band-gap core; and

a curvature trim circuit comprising at least one resistor that is non-linear with temperature.

21. The CMOS voltage reference of claim 20, wherein the slope and level trim circuits sink and/or source current into the band-gap core to adjust the slope and level of an output voltage of the reference.

22. The CMOS voltage reference of claim 21, wherein the nulling amplifier is outside of a signal path of the primary amplifier and nulls offsets and noise associated with the primary amplifier.