Output buffer circuit

• US 6,201,405 B1
• Filed: 05/10/1999
• Issued: 03/13/2001
• Est. Priority Date: 11/12/1996
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Hedberg, Mats
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/307,785
• Time in Patent Office: 673 Days
• Field of Search: 326/30, 326/86, 326/31
• US Class Current: 326/30
• CPC Class Codes: H03K 19/018557 Coupling arrangements; Impedance matching circuits
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

An output buffer circuit for driving a transmission line (7) in accordance with data to be transmitted, comprises a switch stage (1) having an input port (1H, 1L), an output port (OP, ON, OUT) for connection to said transmission line (7) and a control terminal (4). The switch stage comprises switches adapted for connecting the output port with the input port in accordance with a digital input signal (IN). Impedance means (15, 16) are connected to said switch stage (1) and have an impedance control input (C1, C2) for adjusting their impedance in accordance with a control signal. Means are provided for controlling the output impedance of the output port by means of adjusting the impedance of the impedance means (15, 16). A selector circuit (2) selectively connects the output port with a detection input of said controlling means (3), said selector circuit (2) being connected to receive a selection control signal having a fixed timing relationship with said digital input signal.

Claims

1. Output buffer circuit for driving a transmission line (7) in accordance with data to be transmitted, the circuit comprising:

a switch stage (1) having an input port (1H, 1L), a control terminal (4) for receiving a digital input signal (IN) in accordance with data to be transmitted, and an output port for connection to said transmission line (7);

said switch stage (1) comprising switches (11 to 14) adapted for connecting said output port (OP, ON) with said input port (1H, 1L) in accordance with said digital input signal (IN);

impedance means (15, 16) connected to said switch stage (1) and having an impedance control input (C1, C2), an impedance of said impedance means (15, 16) being adjustable in accordance with a control signal applied to said impedance control input (C1, C2);

means (3) for controlling an output impedance of the output port of the switch stage (1) by adjusting of the impedance of said impedance means (15, 16) in accordance with a deviation of a detected output impedance from a desired impedance value;

a selector circuit (2) for selectively connecting said output port (OP, ON) of said switch stage (1) with a detection input of said means for controlling (3); and

said selector circuit (2) being connected to receive a selection control signal having a fixed timing relationship with said digital input signal (IN).

2. An output buffer circuit according to claim 1, characterized in that

said selector circuit (2) is adapted to select between two different modes of connecting said output port of said switch stage (1) to said detection input in accordance with two binary states of said selection control signal.

3. An output buffer circuit according to claim 1, characterized in that

said switch stage (1) comprises a quadruple of switch elements (11 to 14) connected as a bridge, a first diagonal (1H, 1L) of said bridge constituting said input port, a second diagonal (OP, ON) of said bridge constituting said output port;

and

said impedance means (15) comprises

an upper impedance means (15) connected between said input port (1H) and a power supply line (VBH, VBT) for supplying an upper supply potential; and

a lower impedance means (16) connected between said input port (1L) and a power supply line (VBL, GND) for supplying a lower supply potential.

4. An output buffer according to claim 3, characterized in that

said selector circuit (2) is adapted to select that output terminal of said output port (OP, ON) which has a predetermined logic level, for connection with said detection input of said control means (3).

5. An output buffer according to claim 4, characterized in that

said selector circuit (2) comprises a pair of switch elements (21, 22), each switch element being connected between one of the output terminals of said output port (OP, ON) of the switch stage (1) and said detection input of said control means (3);

said switch elements (21, 22) of the pair being connected to receive complementary switching control signals in accordance with the logical state of said digital input signal (IN).

6. An output buffer circuit according to claim 3, characterized in that

said selector circuit (2) is adapted to select that output terminal of said output port (OP, ON) which has a first predetermined logic level, for connection with a first detection input of said control means (3), and to select that output terminal of said output port (OP, ON) which has a logic level complementary to said first logic level, for connection with a second detection input of said control means (3).

7. An output buffer circuit according to claim 6, characterized in that

said selector circuit (2) comprises a quadruple of switch elements (21 to 24) connected as a selector bridge;

a first diagonal (22, 23) of selector switch elements being connected to receive a control signal in accordance with said digital control signal (IN);

a second diagonal (21, 24) of selector switch elements being connected to receive a control signal in complementary relation to said digital control signal (IN).

8. An output buffer circuit according to claim 1, characterized in that

said switch stage (1) comprises a series connection of an upper switch element (11) and a lower switch element (12), connected across the input port (1H, 1L), the output port (OUT) comprising a connection node between the upper and the lower switch element;

and

said impedance means comprises

an upper impedance means (15) connected between said input port (1H) and a power supply line (VBH, VBT) for supplying an upper supply potential; and

a lower impedance means (16) connected between said input port (1L) and a power supply line (VBL, GND) for supplying a lower supply potential.

9. An output buffer circuit according to claim 8, characterized in that

said selector circuit (2) is adapted to connect the output port (OUT) of said switch stage (1) with said detection input of said controlling means (3) and to disconnect the output port (OUT) of said switch stage (1) from said detection input, depending on the logical level of said digital input signal (IN).

10. An output buffer circuit according to claim 9, characterized in that

said selector circuit (2) comprises a switch element (21) connected between an output terminal of said output port (OUT) and said detection input of said control means (3);

said switch element (21) being connected to receive a switching control signal depending on said digital input signal (IN).

11. An output buffer circuit according to claim 9, characterized by

means (25, 26) for holding a signal at said detection input of said impedance control means (3) during a period of time when said selector circuit (2) disconnects said output port from said detection input.

12. An output buffer circuit according to claim 5, characterized in that

said means for controlling (3) comprises a control amplifier (31, 32) connected to receive at its inverting input a reference voltages its non inverting input being connected to receive a detection input signal output by said selector circuit (2);

the output of said control amplifier (31, 32) being connected to control an impedance value of said upper and said lower impedance elements.

13. An output buffer circuit according to claim 12, characterized in that

said upper impedance element (15) comprises a first MOSFET having a first channel width W_ZH;

said lower impedance element (16) comprises a second MOSFET having a channel width (W_ZL) smaller than said first MOSFET;

said output of said control amplifier (31) being connected to a gate of said first MOSFET and a gate of said second MOSFET.

14. An output buffer circuit according to claim 8, characterized in that

said selector circuit (2) is adapted to connect the output port of said switch stage with a first detection input of said controlling means and to disconnect the output port of said switch stage from a second detection input of said impedance controlling means and vice versa, depending on the logical level of said digital input signal.

15. An output buffer circuit according to claim 14, characterized in that

said selector circuit (2) comprises a first switch element (21) connected between an output terminal (OUT) of said output port and said first detection input of said control means (3) and a second switch element (22) connected between said output terminal (OUT) of said output port and said second detection input of said control means (3);

said first and second switch elements (21, 22) being connected to receive switching control signals in complementary relation to each other and depending on said digital input signal (IN).

16. An output buffer circuit according to claim 7, characterized in that said control means (3) comprises

a first control amplifier (31) connected to receive at its inverting input a first reference voltage, its non inverting input being connected to receive a first detection input signal output by said selector circuit (2);

the output of said first control amplifier (31) being connected to control an impedance value of said upper impedance element (15); and

a second control amplifier (32) connected to receive at its inverting input a second reference voltage, its non inverting input being connected to receive a second detection input signal output by said selector circuit (2);

the output of said second control amplifier being connected to control an impedance value of said lower impedance element (16).

17. An output buffer circuit according to claim 16, characterized in that

said upper impedance element (15) and said lower impedance element (16), respectively, comprises a MOSFET connected to receive at its gate an output signal of said first (31) and second (32) control amplifier, respectively.

18. An output buffer circuit for driving a transmission line in accordance with data to be transmitted, the output buffer circuit comprising:

a switch stage having an input port, a control terminal for receiving a digital input signal in accordance with data to be transmitted, and an output port for connection to said transmission line;

said switch stage including at least one switch for connecting said output port with said input port in accordance with said digital input signal;

at least one transistor connected to said switch stage and having an impedance control input, an impedance of said at least one transistor being adjustable in accordance with a control signal applied to said impedance control input;

a controller for controlling an output impedance of the output port of the switch stage by adjusting of the impedance of said at least one transistor in accordance with a deviation of a detected output impedance from a desired impedance value;

a selector circuit for selectively connecting said output port of said switch stage with a detection input of said controller; and

said selector circuit being connected to receive a selection control signal having a fixed timing relationship with said digital input signal.

19. An output buffer circuit according to claim 18, wherein said selector circuit selects between two different modes of connecting said output port of said switch stage to said detection input in accordance with two binary states of said selection control signal.