Pulse width modulation circuit
First Claim
Patent Images
1. A pulse width modulation circuit comprising:
- a clock dividing means for receiving a system clock and generating a plurality of clocks with different clock cycles;
a delaying means for receiving a signal and delaying said signal;
said delaying means having a plurality of delaying elements;
each of said plurality of delaying elements receiving one of said plurality of clocks;
said delaying means receiving a delay data and being responsive to said delay data for selecting a number of said plurality of clocks based on the delay data and activating said respective delaying elements; and
said delaying means being so constructed and arranged to cause the signal to pass through said activated delaying elements and bypass said inactivated delaying elements.
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Abstract
A pulse width modulation circuit utilizes a clock divider to generate a plurality of clocks to be used by a plurality of delay blocks. Each delay block has plurality of delay elements each of which receives one the plurality of clocks. Each delay block receives a delay data, selects a number of the plurality of clocks based on the delay data and activates the respective delay elements for delaying its input signal.
11 Citations
12 Claims
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1. A pulse width modulation circuit comprising:
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a clock dividing means for receiving a system clock and generating a plurality of clocks with different clock cycles;
a delaying means for receiving a signal and delaying said signal;
said delaying means having a plurality of delaying elements;
each of said plurality of delaying elements receiving one of said plurality of clocks;
said delaying means receiving a delay data and being responsive to said delay data for selecting a number of said plurality of clocks based on the delay data and activating said respective delaying elements; and
said delaying means being so constructed and arranged to cause the signal to pass through said activated delaying elements and bypass said inactivated delaying elements. - View Dependent Claims (2, 3)
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4. A pulse width modulation circuit comprising:
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a clock dividing means for receiving a system clock and generating a plurality of clocks with different clock cycles;
a delaying means for receiving a signal having a rising edge and a falling edge and delaying said rising edge of said signal;
said delaying means having a plurality of delaying elements;
each of said plurality of delaying elements receiving one of said plurality of clocks;
said delaying means receiving a delay data and being responsive to said delay data for selecting a number of said plurality of clocks based on the delay data and activating said respective delaying elements;
said delaying means being so constructed and arranged to cause the signal to pass through said activated delaying elements and bypass said inactivated delaying elements; and
said delaying means having a reset means responsive to said falling edge of said signal for resetting said delaying means. - View Dependent Claims (5, 6)
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7. A pulse width modulation circuit comprising:
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a clock dividing means for receiving a system clock and generating a plurality of clocks with different clock cycles;
a plurality of delaying means for receiving a signal and delaying said signal according to a plurality of data;
each of said delaying means having a plurality of delaying elements;
each of said plurality of delaying elements of each delaying means receiving one of said plurality of clocks;
each of said plurality of delaying means receiving one of said plurality of delay data and being responsive to said respective delay data for selecting a number of said plurality of clocks based on the delay data and activating said respective delaying elements; and
each of said delaying means being so constructed and arranged to cause the signal to pass through said respective activated delaying elements and bypass said respective inactivated delaying elements. - View Dependent Claims (8, 9)
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10. A pulse width modulation circuit comprising:
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a clock dividing means for receiving a system clock and generating a plurality of clocks with different clock cycles;
a plurality of delaying means for receiving a signal having a rising edge and a falling edge and delaying said rising edge of said signal according to a plurality of data;
each of said delaying means having a plurality of delaying elements;
each of said plurality of delaying elements of each delaying means receiving one of said plurality of clocks;
each of said plurality of delaying means receiving one of said plurality of delay data and being responsive to said respective delay data for selecting a number of said plurality of clocks based on the delay data and activating said respective delaying elements; and
each of said delaying means being so constructed and arranged to cause the signal to pass through said respective activated delaying elements and bypass said respective inactivated delaying elements; and
said delaying means having a reset means responsive to said falling edge of said signal for resetting said delaying means. - View Dependent Claims (11, 12)
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Specification