Clamped cascode level shifter circuit

• US 6,201,429 B1
• Filed: 05/20/1999
• Issued: 03/13/2001
• Est. Priority Date: 05/20/1999
• Status: Expired due to Fees

• Current Assignee: Golden Long Teng Development Co. Ltd.
• Original Assignee: Analog Microelectronics Incorporated
• Inventors: Rosenthal, Bruce
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/315,666
• Time in Patent Office: 663 Days
• Field of Search: 327/333, 327/199, 327/200, 327/208, 327/209, 327/210, 327/218, 326/80, 326/81, 326/63, 326/68, 326/62
• US Class Current: 327/333
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/01714 by bootstrapping, i.e. by positive feed-back
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

An improved level shifter circuit that toggles a “flying Flip-Flop” comprising a cross-coupled inverter pair with control devices driven out of phase through a pair of cascode transistors. The cross-coupled inverter pair provides pull-up to the positive rail, clamping to a High Side-Common (HSC), and providing Hysteretic Switching. The cascode transistors restrict the pull-down of the control devices, thereby preventing continuous current conduction.

Claims

1. A voltage level shifter circuit comprising:

a first switching device (N1), coupled to receive an input signal (Q);

a first inverter, the first inverter also coupled to receive the input signal Q and generating a first inverter output corresponding to an inverted polarity of the input signal Q;

a second switching device (N2), N2 coupled to the first inverter to receive the inverted polarity of input signal Q; and

a cascode clamp device (P1), P1 being coupled in series between N2 and a flying flip-flop, wherein the flying flip-flop is also coupled to the N1 device to thereby generate a flying flip-flop output signal Q′

that swings between a first voltage source rail voltage and a second voltage signal limited by the cascode clamp P1.

2. The voltage level shifter of claim 1 further comprising a half-bridge circuit, the half-bridge circuit coupled between the flying flip-flop output signal Q′

and the cascode clamp P1 to thereby generate a voltage shifter output signal (Vo) that swings between a positive voltage source rail (VDD) and a ground level.

3. The voltage level shifter of claim 1 further comprising a current boost circuit for faster level shifting, wherein an input of the current boost circuit is coupled to the flying flip-flop and an output is coupled to a high-side switch (N3) for faster half bridge circuit performance.

4. A voltage level shifter circuit comprising:

a first switching device (N1), coupled to receive an input signal (Q);

a first inverter, the first inverter also coupled to receive the input signal Q and generating a first inverter output corresponding to an inverted polarity of the input signal Q;

a second switching device (N2), N2 coupled to the first inverter to receive the inverted polarity of input signal Q;

a cascode clamp device (P1), P1 being coupled in series to N2; and

a flying flip-flop, wherein the flying flip-flop comprises a second inverter coupled at a second inverter input port to the cascode clamp and also coupled in series at a second inverter output port to a third inverter input port, a third inverter output port being also coupled back to the cascode clamp P1 to thereby generate a flying flip-flop output signal Q′

that swings between a first voltage source rail voltage and a second voltage signal limited by the cascode clamp P1.

5. The voltage level shifter of claim 4 further comprising a half-bridge circuit, the half-bridge circuit coupled between the flying flip-flop output signal Q′

and the cascode clamp P1 to thereby generate the voltage shifter output signal (Vo) that swings between a positive voltage source (VDD) and a ground level signal.

6. The voltage level shifter of claim 4 further comprising a current boost circuit for faster level shifting, wherein an input of the current boost circuit is coupled to the flying flip-flop and an output is coupled to a high-side switch (N3) for faster half bridge circuit performance.

7. A voltage level shifter circuit comprising:

a first switching device (N1), N1 comprising a gate input, the gate input coupled to receive an input signal (Q), a drain coupled to an output of a second inverter (V2) and an input of a third inverter (V3), N1 further comprising a source coupled to a ground level;

a first inverter, the first inverter also coupled to receive the input signal Q and generating an output signal equivalent to an inverted polarity of the input signal Q;

a second switching device (N2), N2 comprising a gate input coupled to the first inverter to receive the inverted polarity of input signal Q, a drain coupled to a cascode clamp P1, and a source coupled to the ground level voltage source rail voltage; and

a cascode clamp device (P1), P1 comprises a gate input, a drain, and a source, wherein the drain is coupled in series to the drain of N2, the source coupled to an input of the second inverter and an output of the third inverter, and the gate input coupled to node Vo,

wherein for inverters V2 and V3, each inverter further comprises a pull-up voltage source and a pull-down voltage source input, the pull-up voltage source input coupled to a first voltage source rail voltage, and the pull-down voltage source coupled to the node Vo, to thereby allow Vo to swing between a positive voltage source (VDD) voltage and the ground level.

8. The voltage level shifter of claim 7 further comprising:

a half bridge circuit, the half bridge circuit, coupled to the third inverter, comprising a third switch N3 and a fourth switch N4, wherein each switch comprises a gate input, a source and a drain, with the gate input of N3 being coupled to an output of a fourth inverter V4 and the drain of N3 coupled to the positive voltage source (VDD), and the source coupled to the drain of N4, the gate of N4 coupled to an output of inverter V5, and the source of N4 coupled to the ground level.

9. The voltage level shifter of claim 8 further comprising a boost circuit, coupled to the third inverter, the boost circuit comprising a first diode (D1) and a “

flying capacitor”

(C1), wherein an input of D1 is coupled to the positive VDD voltage source, and an output of D1 coupled to a first port of C1 and a second port of C1 coupled to the source of N3.

10. The voltage level shifter of claim 8 wherein each inverter V4 and V5 comprises an input port, an output port, a pull-up voltage input port, and a pull-down voltage input port,

with the input port of V4 coupled to the source of P1, output port of V4 coupled to the gate input of N3, the pull-up voltage port coupled to the first voltage source rail voltage, and the pull-down voltage port coupled to the node Vo;

and

with the input port of V5 coupled to the output port of the first inverter with the output port of V5 coupled to the gate of N4, the pull-up voltage port of V5 coupled to VDD and the pull-down voltage port coupled to ground level.