Solid state imaging apparatus for imaging a two dimensional optical image having a number of integration circuits

• US 6,201,573 B1
• Filed: 11/27/1996
• Issued: 03/13/2001
• Est. Priority Date: 11/13/1995
• Status: Expired due to Term

• Current Assignee: Hamamatsu Photonics KK
• Original Assignee: Hamamatsu Photonics KK
• Inventors: Mizuno, Seiichiro
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): Vu, Ngoc-Yen, VU, NGOC YEN T
• Application Number:
  US08/757,423
• Time in Patent Office: 1,567 Days
• Field of Search: H04/N.314, 250/208.1, 348/294, 348/300, 348/301, 348/302, 348/303, 348/304, 348/307-311, 348/315, 348/316, 348/317, 348/319-323
• US Class Current: 348/308
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 3/1512 for MOS image-sensors, e.g. MOS-CCD H04N3/1581 takes precedence
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

In a solid-state imaging apparatus of the present invention, after an integration operation is started with an integration circuit by setting a reset instruction signal at logical zero, charges stored in a light receiving device are discharged by selecting this light receiving device. A value of an integration signal obtained by an integration operation of an integration circuit is compared with a reference value by a comparing circuit. A capacitance control section informs a capacitance instruction signal to a variable capacitor section of the integration circuit in response to a comparing result. A feedback loop is formed, which consists of the integration circuit, the comparing circuit, and a capacitance control circuit. When the value of the integration signal agrees finally with the reference value within resolution, the capacitance control section outputs a value in accordance with the capacitance instruction signal. This value is sequentially read out through a horizontal reading-out section.

Claims

1. A solid-state imaging apparatus for imaging a two-dimensional optical image comprising:

a light receiving unit including a first number of vertical light receiving sections arranged along a first direction, each of the vertical light receiving sections including a second number of light receiving devices arranged in a second direction, each of the light receiving device being composed of a photoelectric conversion element for converting an input optical signal to a current signal and a switching element, the switching element having a first terminal connected to a signal output terminal of the photoelectric conversion element and a second terminal to output the current signal generated by the photoelectric conversion element in response to a vertical scanning signal, and each of said vertical light receiving sections having a signal output terminal electrically connected to the second terminal of said switching element;

a first number of integration circuits for receiving individually an output signal from the corresponding vertical light receiving section, each of the integration circuits enabling, in response to a reset instruction signal, a variable capacitor section either to perform an integration for the current signal output from corresponding vertical light receiving section or not to perform the integration for the current signal, said variable capacitor section being connected between input and output terminals of a charge amplifier, and the variable capacitor section varying a capacitance value in response to a capacitance instruction signal;

the first number of comparing circuits for comparing an integration signal output from the corresponding integration circuit with a reference value to output a comparing result;

the first number of capacitance control sections, each receiving a comparing result signal from the corresponding comparing circuit and for outputting a capacitance instruction signal for informing a capacitance variation value to said variable capacitor section in accordance with a value of the comparing result signal, and outputting a first digital signal in response to said capacitance instruction signal when it is judged from said comparing result signal that a value of the integration signal agrees with said reference value at a predetermined resolution; and

the first number of horizontal reading-out sections, each receiving said first digital signal from the corresponding capacitance control section, and outputting a second digital signal in response to a horizontal scanning signal.

2. The imaging apparatus according to claim 1, wherein values of the first and second digital signals are equal each other.

3. The imaging apparatus according to claim 1, wherein said horizontal reading-out section further comprises a data conversion section for receiving said first digital signal output from said capacitance control section and for outputting said second digital signal after data conversion.

4. The imaging apparatus according to claim 3, wherein said data conversion section has an offset cancel.

5. The imaging apparatus according to claim 3, wherein said data conversion section comprises a read-only memory device for receiving said first digital signal at an address input terminal thereof, performing data conversion based on data written to a memory section thereof, and outputting said second digital signal from a data output terminal thereof.

6. The imaging apparatus according to claims 1, wherein said variable capacitor section comprises:

a third number of capacitance elements;

the third number of first switching elements, each of the first switching elements having a first terminal connected to a first terminal of corresponding one of the capacitance elements and having a second terminal connected to the output terminal of said charge amplifiers, and each first switching element opening/closing in response to said capacitance instruction signal; and

the third number of second switching elements, each of the second switching elements having a first terminal connected to a second terminal of corresponding one of the capacitance elements and having a second terminal connected to a reference potential level terminal, and each second switching element opening/closing in response to a value of the capacitance instruction signal.

7. The imaging apparatus according to claim 6, wherein a resolution is equal to ½

<sup>(the third number−

1)</sup> of said reference value, and each of the third number of the capacitance elements has a capacitance value satisfying a relationship expressed by an equation

8. A solid-state imaging apparatus for imaging a two-dimensional optical image comprising:

a light receiving unit including a first number of vertical light receiving sections arranged along a first direction, each of the vertical light receiving sections including a second number of light receiving devices arranged in a second direction, each light receiving device being composed of a photoelectric conversion element for converting an input optical signal to a current signal and a switching element, the switching element having a first terminal connected to a signal output terminal of said photoelectric conversion element and a second terminal to output the current signal generated by said photoelectric conversion element in response to a vertical scanning signal, and each of said vertical light receiving sections having a signal output terminal electrically connected to a second terminal of said switching element;

a first number of integration circuits for receiving individually the output signal from the corresponding vertical light receiving section, each of the integration circuits enabling, in response to a reset instruction signal, a variable capacitor section either to perform an integration for the current signal output from corresponding vertical light receiving section or not to perform the integration for the current signal, said variable capacitor section being connected between input and output terminals of a charge amplifier, and the variable capacitor section varying a capacitance value in response to a capacitance instruction signal;

the first number of comparing circuits, each comparing the value of the integration signal from corresponding one of said integration circuits with a reference value every time when a capacitance value of the variable capacitor section of corresponding one of said integration circuits varies and outputting a comparing result as a first serial digital data;

the first of capacitance control sections, each receiving a comparing result signal from corresponding one of said comparing circuits, and outputting a capacitance instruction signal for instructing said variable capacitor section according to the value of the comparing result signal;

the first number of first-in-last-out (FILO registers, each sequentially receiving the first serial digital data from corresponding one of said comparing circuits, and outputting a second serial digital data in an reverse order to the inputting order;

the first number of processing units, each receiving sequentially said second serial digital data from corresponding one of said FILO registers, and outputting a first parallel digital signal after parallel processing; and

the first number of horizontal reading-out sections, each receiving a signal from corresponding one of said processing units, and outputting the signal in response to a horizontal scanning signal.

9. The imaging apparatus according to claim 8, wherein said processing unit further receives said second serial digital data from a FILO register arranged in an adjacent vertical light receiving section, and performs computations for adjacent pixels to output a second parallel digital data to said horizontal reading-out section.

10. The imaging apparatus according to claims 8, wherein said variable capacitor section comprises:

a third number of capacitance elements;

the third number of first switching elements, each of the first switching elements having a first terminal connected to a first terminal of corresponding one of the capacitance elements and having a second terminal connected to the output terminal of said charge amplifiers, each of the first switching elements opening/closing in response to said capacitance instruction signal; and

the third number of second switching elements, each of the second switching elements having a first terminal connected to a second terminal of corresponding one of the capacitance elements and having a second terminal connected to a reference potential level terminal, each of the second switching elements opening/closing in response to a value of the capacitance instruction signal.

11. The imaging apparatus according to claim 10, wherein a resolution is equal to ½

<sup>(the third number−

1)</sup> of said reference value, and each of the third number of the capacitance elements has a capacitance value satisfying a relationship expressed by an equation