Electronic memory with disturb prevention function
First Claim
Patent Images
1. A destructive readout, nonvolatile memory system comprising:
- a power source for applying electrical power to said memory system;
a destructive readout, nonvolatile memory cell for holding data;
an electronic circuit selected from the group consisting of;
a rewrite circuit for rewriting said data to said memory after it has been read;
a data storage element for holding said data to be rewritten to said memory; and
a power on reset circuit for resetting logic in said memory system when said voltage drops below an OFF threshold and then rises to an ON threshold; and
a disturb prevention circuit for controlling at least one of said power source and said electronic circuits to prevent said data from being disturbed during a period when said electrical power is unstable.
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Abstract
A ferroelectric destructive read-out memory system includes a power source, a memory array including a memory cell, and a logic circuit for applying a signal to the memory array. Whenever a low power condition is detected in said power source, a disturb prevent circuit prevents unintended voltages due to the low power condition from disturbing the memory cell. The disturb prevent circuit also stops the operation of the logic circuit for a time sufficient to permit a rewrite cycle to be completed, thereby preventing loss of the data being rewritten.
80 Citations
45 Claims
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1. A destructive readout, nonvolatile memory system comprising:
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a power source for applying electrical power to said memory system;
a destructive readout, nonvolatile memory cell for holding data;
an electronic circuit selected from the group consisting of;
a rewrite circuit for rewriting said data to said memory after it has been read;
a data storage element for holding said data to be rewritten to said memory; and
a power on reset circuit for resetting logic in said memory system when said voltage drops below an OFF threshold and then rises to an ON threshold; and
a disturb prevention circuit for controlling at least one of said power source and said electronic circuits to prevent said data from being disturbed during a period when said electrical power is unstable.
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2. A ferroelectric memory system comprising:
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a power source for applying electrical power to said memory system;
a memory cell for holding data, said memory cell including a ferroelectric material;
a conductor selected from the group consisting of a bit line and a plate line; and
a disturb prevention circuit for preventing signals that can disturb said data from being placed on said conductor during a period when said electrical power is unstable. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A destructive readout memory system comprising:
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a power source for applying electrical power to said memory system;
a destructive readout memory cell for holding data;
a logic circuit for writing, reading, and rewriting data into said memory cell; and
a disturb prevention circuit for preventing said data from being disturbed due to a condition in which said electrical power is unstable;
said disturb prevention circuit comprising a circuit communicating with said logic circuit for preventing said rewriting of said data from being disturbed due to said condition.- View Dependent Claims (27)
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28. A ferroelectric memory system comprising:
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a power source for applying electrical power to said memory system;
a memory cell for holding data, said memory cell including a ferroelectric material;
a logic circuit for writing, reading, and rewriting data into said memory cell; and
a disturb prevention circuit for preventing said data from being disturbed due to a condition in which said electrical power is unstable;
said disturb prevention circuit comprising a circuit communicating with said logic circuit for preventing said rewriting of said data from being disturbed due to said condition.- View Dependent Claims (29, 30, 37, 38, 39)
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31. A ferroelectric memory system comprising:
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a power source for applying electrical power to said memory system;
a memory cell for holding data, said memory cell including a ferroelectric material; and
a disturb prevention circuit for preventing said data from being disturbed due to a condition in which said electrical power is unstable;
wherein;
said power source comprises a source of a voltage;
said memory system further includes a memory array and said memory cell is part of said memory array;
said memory system further includes a logic circuit for applying an electrical signal to said memory array and a power-on-reset circuit for resetting said logic circuit when said voltage drops below an OFF threshold then rises to an ON threshold; and
said disturb prevention circuit comprises a circuit for preventing said resetting of said logic circuit from causing loss of said data.- View Dependent Claims (32)
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33. A ferroelectric memory system comprising:
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a power source for applying electrical power to said memory system;
a memory cell for holding data, said memory cell including a ferroelectric material; and
a disturb prevention circuit for preventing said data from being disturbed due to a condition in which said electrical power is unstable;
wherein said memory system includes a timing signal generator and said disturb prevention circuit comprises a pause signal generating circuit for generating a pause signal for preventing said timing signal generator from outputting signals that could result in loss of said data. - View Dependent Claims (34, 35)
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36. A ferroelectric memory system comprising:
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a power source for applying electrical power to said memory system;
a memory cell for holding data, said memory cell including a ferroelectric material; and
a disturb prevention circuit for preventing said data from being disturbed due to a condition in which said electrical power is unstable;
wherein said memory system includes a data storage element and said disturb prevention circuit comprises a freeze circuit for freezing the data content of said data storage element while a predetermined signal is applied to said freeze circuit.
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40. A method of operating a destructive readout, nonvolatile memory having:
- a memory cell in which data is stored; and
an electronic circuit selected from the group consisting of;
a rewrite circuit for rewriting said data to said memory after it has been read;
a data storage element for holding said data to be rewritten to said memory; and
a power on reset circuit for resetting logic in said memory system when said voltage drops below an OFF threshold and then rises to an ON threshold;
said method comprising the steps of;sensing a low power condition of said memory; and
controlling at least one of said power source and said electronic circuits to Prevent unintended voltages produced by said low power condition from disturbing said data in said memory cell.
- a memory cell in which data is stored; and
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41. A method of operating a ferroelectric memory having a memory cell in which data is stored, and a conductor selected from the group consisting of a bit line and a plate line;
- said method comprising the steps of;
sensing a low power condition of said memory; and
preventing unintended voltages produced by said low power condition from being placed on said conductor. - View Dependent Claims (42, 43, 44, 45)
receiving a memory control signal; and
disabling said memory signal for a time period in which said low power condition could cause said unintended voltages.
- said method comprising the steps of;
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45. A method as in claim 41 wherein said memory includes a logic circuit for applying a signal to said memory cell, and said step of preventing comprises stopping the operation of said logic circuit for a time period in which said low power condition could cause said unintended voltages.
Specification