Programmable impedance device

• US 6,201,734 B1
• Filed: 09/25/1998
• Issued: 03/13/2001
• Est. Priority Date: 09/25/1998
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Sansbury, James D., Wang, Sau C.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/159,848
• Time in Patent Office: 900 Days
• Field of Search: 365/185.1, 365/185.01, 365/185.03, 365/185.19, 365/185.08
• US Class Current: 365/185.1
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates

Abstract

A programmable impedance element (204) is implemented using integrated circuit techniques and devices. An impedance of the programmable impedance element is adjusted by appropriately configuring the element. The programmable impedance element has a range of impedance values, and is configurable to be a value within this range. In an embodiment, the programmable impedance element is implemented using a floating gate device (230), and is nonvolatile.

Claims

1. A circuit comprising:

a memory device coupled between a bit line and a source line; and

a programmable impedance device coupled to the memory device, wherein an impedance between a first terminal and a second terminal of the programmable impedance device is configurable to be one of at least three different values depending on a configured state of the memory device.

2. The circuit of claim 1 wherein the memory device and programmable impedance device share a floating gate.

3. The circuit of claim 1 wherein the memory device is a floating gate memory cell.

4. The circuit of claim 1 wherein the memory device is selected from the group consisting of p-channel floating gate transistors, n-channel floating gate transistors, Flash transistors, EEPROM transistors, multilevel memory cells, and analog memory cells.

5. The circuit of claim 1 wherein the programmable impedance device is a p-channel device, n-channel device, MOS device, PMOS transistor, NMOS transistor, or depletion device.

6. The circuit of claim 1 wherein the programmable impedance device is configurable to have at least 256 different impedance values.

7. The circuit of claim 1 wherein the memory device is a Flash memory cell, configurable by hot election programming.

8. The circuit of claim 1 wherein the impedance of the programmable impedance device increases as a programmed threshold voltage of the memory device increases.

9. The circuit of claim 1 wherein a programming voltage applied to a control gate of the memory device has an approximately linear relationship with a resulting programmed threshold voltage of the memory device.

10. The circuit of claim 1 wherein the memory device is configurable to have one of 256 different threshold voltages.

11. A network comprising series or parallel interconnections of multiple instances of the circuit recited in claim 1.

12. A voltage bias generator comprising a circuit as recited in claim 1.

13. The circuit of claim 1 wherein during a normal operation state, a bias voltage is applied to a control gate of the programmable impedance device to adjust the impedance.

28. The circuit of claim 24 wherein the nonvolatile programmable impedance element comprises the circuit as recited in claim 1.

14. A method of selecting a value of an impedance on an integrated circuit comprising:

applying a programming voltage to a floating gate memory device;

configuring the floating gate memory device to have a programmed threshold voltage that is a value between a first threshold voltage and a second threshold voltage, inclusive; and

obtaining an impedance value for a programmable impedance device, coupled to the floating gate memory device, based on the threshold voltage of the floating gate memory device.

15. The method of claim 14 wherein a floating gate is shared between the floating gate memory device and the programmable impedance device.

16. The method of claim 14 wherein a relationship between a level of the applied programming voltage and the programmed threshold voltage is approximately linear.

17. The method of claim 14 wherein the first threshold voltage is a threshold voltage of an unprogrammed floating gate memory device.

18. A programmable impedance element comprising:

a memory cell comprising a floating gate, wherein the memory cell is configurable to have more than two threshold voltages; and

a programmable impedance device sharing the floating gate, wherein an impedance of the programmable impedance device is based on a threshold voltage of the memory cell.

19. The programmable impedance element of claim 18 wherein the memory cell and programmable impedance device are n-channel devices or p-channel devices.

20. The programmable impedance element of claim 18 wherein the threshold voltage of the memory cell is adjusted by a number of pulses of a programming voltage applied at a control gate of the memory cell.

21. The programmable impedance element of claim 18 wherein the threshold voltage of the memory cell is adjusted by a number of pulses of a programming voltage applied at a bit line of the memory cell.

22. The programmable impedance element of claim 18 wherein the memory cell is configurable to have one of at least 256 different threshold voltage levels.

23. The programmable impedance element of claim 18 wherein the programmable impedance device is configurable to have at least 256 different impedance values.

29. The circuit of claim 24 wherein the nonvolatile programmable impedance element comprises the circuit as recited in claim 18.

24. A circuit comprising:

a nonvolatile programmable impedance element coupled between an input node and an output node, wherein the nonvolatile programmable impedance element provides an impedance value selectable by configuring a floating gate; and

a capacitor coupled between the output node and a reference potential, wherein the circuit provides a delay based on the impedance of the nonvolatile programmable impedance element.

25. The circuit of claim 24 wherein the nonvolatile programmable impedance element comprises a Flash cell, EPROM cell, or EEPROM cell.

26. The circuit of claim 24 wherein the capacitor is implemented using parasitic capacitance.

27. The circuit of claim 24 wherein the capacitor is implemented using a MOS transistor.

30. The circuit of claim 24 wherein the nonvolatile programmable impedance element comprises a multilevel memory cell or an analog memory cell.