Field effect transistor with controlled body bias

• US 6,201,761 B1
• Filed: 01/26/2000
• Issued: 03/13/2001
• Est. Priority Date: 01/26/2000
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wollesen, Donald L.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US09/491,823
• Time in Patent Office: 412 Days
• Field of Search: 365/51, 365/185.33, 365/189.01, 365/176, 365/181, 365/185.29
• US Class Current: 365/233.15
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. A clock signal defines a clock period with an active portion and a wait portion. The source region and/or the drain region are coupled to a body pumping signal. The body pumping signal includes a negative voltage pulse occurring during the wait portion which sets the voltage of a body region of the FET to a preset voltage during such negative voltage pulse. Decay of the preset voltage is predictable such that operation of the FET can be controlled during the active portion.

Claims

1. A silicon-on-insulator logic circuit with controlled field effect transistor body potential, comprising:

a) a silicon-on-insulator substrate with a silicon device layer separated from a base substrate by an insulating layer;

b) a field effect transistor formed in the silicon device layer including a source region and a drain region both of a first semiconductor conductivity, a gate electrode defining an electrically isolated central channel region of the opposite semiconductor conductivity between the source region and the drain region;

c) a clock signal defining a clock period with an active portion and a wait portion; and

d) a charge pump voltage signal comprising a negative voltage pulse dropping the signal potential of the charge pump signal to a pump potential and occurring during a portion of the wait portion of the clock period and coupled to at least one of the source region and drain region to drop the potential of such at least one of the source region and the drain region to the pump potential during the negative voltage pulse to create a forward bias junction between the at least one of a source region and drain region and the body region to drop the potential in the body region to a preset potential.

2. The silicon-on-insulator logic circuit with controlled field effect transistor body potential of claim 1, further including a switch coupled between the at least one of the source region and the drain region and the charge pump voltage signal and driven by the clock signal to isolate the at least one of the source region and the drain region from the charge pump signal during the active portion of the clock period.

3. The silicon-on-insulator logic circuit with controlled field effect transistor body potential of claim 2, wherein the field effect transistor operates in a voltage range between a ground voltage and a first positive voltage and the signal potential is approximately ground voltage and the pump potential is less than ground.

4. The silicon-on-insulator logic circuit with controlled field effect transistor body potential of claim 2, wherein the pump potential is approximately five volts less than ground potential.

5. The silicon-on-insulator logic circuit with controlled field effect transistor body potential of claim 1, further including a capacitor coupled between the at least one of the source region and the drain region and the charge pump voltage signal.

6. The silicon-on-insulator logic circuit with controlled field effect transistor body potential of claim 5, wherein the field effect transistor operates in a voltage range between a ground voltage and a first positive voltage and the signal potential is a positive voltage and the pump potential is approximately ground.

7. The silicon-on-insulator logic circuit with controlled field effect transistor body potential of claim 6, wherein the field effect transistor and the capacitor comprise a dynamic memory cell.

8. A method of controlling the floating body potential of a silicon on insulator field effect transistor, comprising:

a) generating a clock signal to define a clock period with an active portion and a wait portion; and

(b) coupling at least one of a source region and a drain region of said field effect transistor to a body pumping voltage pulse during a portion of the wait portion to create a forward biased junction between a body region of said field effect transistor and the at least one of the source region and the drain region to sink a body potential to a known potential during the portion of the wait portion.

9. The method of controlling the floating body potential of a silicon on insulator field effect transistor of claim 8, wherein the body pumping voltage pulse is a voltage pulse in a body pumping signal and further including isolating the at least one of a source region and a drain region from the body pumping signal during the active portion.

10. The method of controlling the floating body potential of a silicon on insulator field effect transistor of claim 9, wherein the field effect transistor operates in a voltage range between a ground voltage and a first positive voltage and the body pumping voltage signal potential is approximately ground voltage and the body pumping voltage pulse is less than ground.

11. The method of controlling the floating body potential of a silicon on insulator field effect transistor of claim 10, wherein the body pumping voltage pulse potential is approximately five volts less than ground potential.

12. The method of controlling the floating body potential of a silicon on insulator field effect transistor of claim 8, wherein the body pumping voltage pulse is a voltage pulse in a body pumping signal and further includes capacitively coupling the at least one of a source region and a drain region to the body pumping signal during the active portion.

13. The method of controlling the floating body potential of a silicon on insulator field effect transistor of claim 12, wherein the field effect transistor operates in a voltage range between a ground voltage and a first positive voltage and the body pumping signal potential is a positive voltage and the body pumping pulse potential is approximately ground.

14. The method of controlling the floating body potential of a silicon on insulator field effect transistor of claim 13, wherein the field effect transistor and a capacitor forming the capacitive coupling form a dynamic memory cell.

15. A static random access memory cell, comprising:

a) a silicon-on-insulator substrate with a silicon device layer separated from a base substrate by an insulating layer;

b) a plurality of field effect transistor formed in the silicon device layer including a source region and a drain region both of a first semiconductor conductivity, a gate electrode defining an electrically isolated central channel region of the opposite semiconductor conductivity between the source region and the drain region;

c) SRAM circuitry interconnecting the source regions, drain region, and gate electrode of each field effect transistor to form an SRAM cell;

d) a clock signal defining a clock period with an active portion and a wait portion; and

d) a charge pump voltage signal comprising a negative voltage pulse dropping the signal potential of the charge pump signal to a pump potential and occurring during a portion of the wait portion of the clock period and coupled to at least one of the source region and drain region of at least one of the field effect transistors to drop the potential of at least one of the source region and the drain region to the pump potential during the negative voltage pulse to create a forward bias junction between the at least one of a source region and drain region and the body region to drop the potential in the body region to a preset potential.

16. The static random access memory cell of claim 15, further including a switch coupled between the at least one of the source region and the drain region and the charge pump voltage signal and driven by the clock signal to isolate the at least one of the source region and the drain region from the charge pump signal during the active portion of the clock period.

17. The static random access memory cell claim 16, wherein the field effect transistor operates in a voltage range between a ground voltage and a first positive voltage and the signal potential is approximately ground voltage and the pump potential is less than ground.

18. The static random access memory cell claim 17, wherein the pump potential is approximately five volts less than ground potential.

19. The static random access memory cell of claim 18, further including a capacitor coupled between the at least one of the source region and the drain region and the charge pump voltage signal.

20. The static random access memory cell of claim 19, wherein the field effect transistor operates in a voltage range between a ground voltage and a first positive voltage and the signal potential is a positive voltage and the pump potential is approximately ground.